9a8fd55899
The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
28 lines
805 B
C
28 lines
805 B
C
/*
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* include/asm-xtensa/hardirq.h
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of
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* this archive for more details.
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*
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* Copyright (C) 2002 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_HARDIRQ_H
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#define _XTENSA_HARDIRQ_H
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#include <linux/config.h>
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#include <linux/cache.h>
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#include <asm/irq.h>
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/* headers.S is sensitive to the offsets of these fields */
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typedef struct {
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unsigned int __softirq_pending;
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unsigned int __syscall_count;
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struct task_struct * __ksoftirqd_task; /* waitqueue is too large */
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unsigned int __nmi_count; /* arch dependent */
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} ____cacheline_aligned irq_cpustat_t;
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#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
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#endif /* _XTENSA_HARDIRQ_H */
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