e0a593104d
Customize the SEC interrupt priority array in machine ints-priority.c. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bob Liu <lliubbo@gmail.com>
156 lines
3.6 KiB
C
156 lines
3.6 KiB
C
/*
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* Copyright 2007-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*
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* Set up the interrupt priorities
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <asm/blackfin.h>
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u8 sec_int_priority[] = {
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255, /* IRQ_SEC_ERR */
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255, /* IRQ_CGU_EVT */
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254, /* IRQ_WATCH0 */
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254, /* IRQ_WATCH1 */
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253, /* IRQ_L2CTL0_ECC_ERR */
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253, /* IRQ_L2CTL0_ECC_WARN */
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253, /* IRQ_C0_DBL_FAULT */
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253, /* IRQ_C1_DBL_FAULT */
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252, /* IRQ_C0_HW_ERR */
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252, /* IRQ_C1_HW_ERR */
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255, /* IRQ_C0_NMI_L1_PARITY_ERR */
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255, /* IRQ_C1_NMI_L1_PARITY_ERR */
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50, /* IRQ_TIMER0 */
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50, /* IRQ_TIMER1 */
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50, /* IRQ_TIMER2 */
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50, /* IRQ_TIMER3 */
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50, /* IRQ_TIMER4 */
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50, /* IRQ_TIMER5 */
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50, /* IRQ_TIMER6 */
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50, /* IRQ_TIMER7 */
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50, /* IRQ_TIMER_STAT */
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0, /* IRQ_PINT0 */
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0, /* IRQ_PINT1 */
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0, /* IRQ_PINT2 */
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0, /* IRQ_PINT3 */
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0, /* IRQ_PINT4 */
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0, /* IRQ_PINT5 */
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0, /* IRQ_CNT */
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50, /* RQ_PWM0_TRIP */
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50, /* IRQ_PWM0_SYNC */
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50, /* IRQ_PWM1_TRIP */
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50, /* IRQ_PWM1_SYNC */
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0, /* IRQ_TWI0 */
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0, /* IRQ_TWI1 */
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10, /* IRQ_SOFT0 */
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10, /* IRQ_SOFT1 */
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10, /* IRQ_SOFT2 */
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10, /* IRQ_SOFT3 */
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0, /* IRQ_ACM_EVT_MISS */
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0, /* IRQ_ACM_EVT_COMPLETE */
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0, /* IRQ_CAN0_RX */
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0, /* IRQ_CAN0_TX */
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0, /* IRQ_CAN0_STAT */
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100, /* IRQ_SPORT0_TX */
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100, /* IRQ_SPORT0_TX_STAT */
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100, /* IRQ_SPORT0_RX */
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100, /* IRQ_SPORT0_RX_STAT */
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100, /* IRQ_SPORT1_TX */
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100, /* IRQ_SPORT1_TX_STAT */
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100, /* IRQ_SPORT1_RX */
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100, /* IRQ_SPORT1_RX_STAT */
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100, /* IRQ_SPORT2_TX */
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100, /* IRQ_SPORT2_TX_STAT */
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100, /* IRQ_SPORT2_RX */
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100, /* IRQ_SPORT2_RX_STAT */
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0, /* IRQ_SPI0_TX */
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0, /* IRQ_SPI0_RX */
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0, /* IRQ_SPI0_STAT */
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0, /* IRQ_SPI1_TX */
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0, /* IRQ_SPI1_RX */
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0, /* IRQ_SPI1_STAT */
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0, /* IRQ_RSI */
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0, /* IRQ_RSI_INT0 */
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0, /* IRQ_RSI_INT1 */
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0, /* DMA11 Data (SDU) */
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0, /* DMA12 Data (Reserved) */
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0, /* Reserved */
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0, /* Reserved */
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30, /* IRQ_EMAC0_STAT */
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0, /* EMAC0 Power (Reserved) */
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30, /* IRQ_EMAC1_STAT */
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0, /* EMAC1 Power (Reserved) */
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0, /* IRQ_LP0 */
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0, /* IRQ_LP0_STAT */
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0, /* IRQ_LP1 */
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0, /* IRQ_LP1_STAT */
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0, /* IRQ_LP2 */
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0, /* IRQ_LP2_STAT */
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0, /* IRQ_LP3 */
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0, /* IRQ_LP3_STAT */
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0, /* IRQ_UART0_TX */
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0, /* IRQ_UART0_RX */
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0, /* IRQ_UART0_STAT */
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0, /* IRQ_UART1_TX */
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0, /* IRQ_UART1_RX */
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0, /* IRQ_UART1_STAT */
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0, /* IRQ_MDMA0_SRC_CRC0 */
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0, /* IRQ_MDMA0_DEST_CRC0 */
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0, /* IRQ_CRC0_DCNTEXP */
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0, /* IRQ_CRC0_ERR */
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0, /* IRQ_MDMA1_SRC_CRC1 */
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0, /* IRQ_MDMA1_DEST_CRC1 */
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0, /* IRQ_CRC1_DCNTEXP */
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0, /* IRQ_CRC1_ERR */
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0, /* IRQ_MDMA2_SRC */
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0, /* IRQ_MDMA2_DEST */
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0, /* IRQ_MDMA3_SRC */
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0, /* IRQ_MDMA3_DEST */
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120, /* IRQ_EPPI0_CH0 */
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120, /* IRQ_EPPI0_CH1 */
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120, /* IRQ_EPPI0_STAT */
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120, /* IRQ_EPPI2_CH0 */
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120, /* IRQ_EPPI2_CH1 */
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120, /* IRQ_EPPI2_STAT */
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120, /* IRQ_EPPI1_CH0 */
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120, /* IRQ_EPPI1_CH1 */
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120, /* IRQ_EPPI1_STAT */
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120, /* IRQ_PIXC_CH0 */
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120, /* IRQ_PIXC_CH1 */
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120, /* IRQ_PIXC_CH2 */
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120, /* IRQ_PIXC_STAT */
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120, /* IRQ_PVP_CPDOB */
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120, /* IRQ_PVP_CPDOC */
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120, /* IRQ_PVP_CPSTAT */
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120, /* IRQ_PVP_CPCI */
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120, /* IRQ_PVP_STAT0 */
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120, /* IRQ_PVP_MPDO */
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120, /* IRQ_PVP_MPDI */
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120, /* IRQ_PVP_MPSTAT */
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120, /* IRQ_PVP_MPCI */
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120, /* IRQ_PVP_CPDOA */
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120, /* IRQ_PVP_STAT1 */
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0, /* IRQ_USB_STAT */
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0, /* IRQ_USB_DMA */
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0, /* IRQ_TRU_INT0 */
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0, /* IRQ_TRU_INT1 */
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0, /* IRQ_TRU_INT2 */
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0, /* IRQ_TRU_INT3 */
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0, /* IRQ_DMAC0_ERROR */
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0, /* IRQ_CGU0_ERROR */
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0, /* Reserved */
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0, /* IRQ_DPM */
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0, /* Reserved */
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0, /* IRQ_SWU0 */
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0, /* IRQ_SWU1 */
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0, /* IRQ_SWU2 */
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0, /* IRQ_SWU3 */
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0, /* IRQ_SWU4 */
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0, /* IRQ_SWU4 */
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0, /* IRQ_SWU6 */
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};
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