0a625fd2ab
Current deficiencies: 1) No HMAC hash support yet. 2) Although the algs are registered as ASYNC they always run synchronously. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
231 lines
6.1 KiB
C
231 lines
6.1 KiB
C
#ifndef _N2_CORE_H
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#define _N2_CORE_H
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#ifndef __ASSEMBLY__
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struct ino_blob {
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u64 intr;
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u64 ino;
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};
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struct spu_mdesc_info {
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u64 cfg_handle;
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struct ino_blob *ino_table;
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int num_intrs;
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};
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struct n2_crypto {
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struct spu_mdesc_info cwq_info;
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struct list_head cwq_list;
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};
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struct n2_mau {
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struct spu_mdesc_info mau_info;
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struct list_head mau_list;
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};
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#define CWQ_ENTRY_SIZE 64
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#define CWQ_NUM_ENTRIES 64
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#define MAU_ENTRY_SIZE 64
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#define MAU_NUM_ENTRIES 64
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struct cwq_initial_entry {
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u64 control;
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u64 src_addr;
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u64 auth_key_addr;
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u64 auth_iv_addr;
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u64 final_auth_state_addr;
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u64 enc_key_addr;
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u64 enc_iv_addr;
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u64 dest_addr;
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};
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struct cwq_ext_entry {
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u64 len;
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u64 src_addr;
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u64 resv1;
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u64 resv2;
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u64 resv3;
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u64 resv4;
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u64 resv5;
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u64 resv6;
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};
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struct cwq_final_entry {
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u64 control;
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u64 src_addr;
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u64 resv1;
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u64 resv2;
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u64 resv3;
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u64 resv4;
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u64 resv5;
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u64 resv6;
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};
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#define CONTROL_LEN 0x000000000000ffffULL
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#define CONTROL_LEN_SHIFT 0
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#define CONTROL_HMAC_KEY_LEN 0x0000000000ff0000ULL
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#define CONTROL_HMAC_KEY_LEN_SHIFT 16
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#define CONTROL_ENC_TYPE 0x00000000ff000000ULL
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#define CONTROL_ENC_TYPE_SHIFT 24
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#define ENC_TYPE_ALG_RC4_STREAM 0x00ULL
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#define ENC_TYPE_ALG_RC4_NOSTREAM 0x04ULL
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#define ENC_TYPE_ALG_DES 0x08ULL
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#define ENC_TYPE_ALG_3DES 0x0cULL
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#define ENC_TYPE_ALG_AES128 0x10ULL
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#define ENC_TYPE_ALG_AES192 0x14ULL
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#define ENC_TYPE_ALG_AES256 0x18ULL
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#define ENC_TYPE_ALG_RESERVED 0x1cULL
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#define ENC_TYPE_ALG_MASK 0x1cULL
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#define ENC_TYPE_CHAINING_ECB 0x00ULL
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#define ENC_TYPE_CHAINING_CBC 0x01ULL
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#define ENC_TYPE_CHAINING_CFB 0x02ULL
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#define ENC_TYPE_CHAINING_COUNTER 0x03ULL
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#define ENC_TYPE_CHAINING_MASK 0x03ULL
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#define CONTROL_AUTH_TYPE 0x0000001f00000000ULL
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#define CONTROL_AUTH_TYPE_SHIFT 32
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#define AUTH_TYPE_RESERVED 0x00ULL
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#define AUTH_TYPE_MD5 0x01ULL
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#define AUTH_TYPE_SHA1 0x02ULL
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#define AUTH_TYPE_SHA256 0x03ULL
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#define AUTH_TYPE_CRC32 0x04ULL
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#define AUTH_TYPE_HMAC_MD5 0x05ULL
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#define AUTH_TYPE_HMAC_SHA1 0x06ULL
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#define AUTH_TYPE_HMAC_SHA256 0x07ULL
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#define AUTH_TYPE_TCP_CHECKSUM 0x08ULL
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#define AUTH_TYPE_SSL_HMAC_MD5 0x09ULL
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#define AUTH_TYPE_SSL_HMAC_SHA1 0x0aULL
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#define AUTH_TYPE_SSL_HMAC_SHA256 0x0bULL
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#define CONTROL_STRAND 0x000000e000000000ULL
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#define CONTROL_STRAND_SHIFT 37
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#define CONTROL_HASH_LEN 0x0000ff0000000000ULL
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#define CONTROL_HASH_LEN_SHIFT 40
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#define CONTROL_INTERRUPT 0x0001000000000000ULL
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#define CONTROL_STORE_FINAL_AUTH_STATE 0x0002000000000000ULL
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#define CONTROL_RESERVED 0x001c000000000000ULL
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#define CONTROL_HV_DONE 0x0004000000000000ULL
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#define CONTROL_HV_PROTOCOL_ERROR 0x0008000000000000ULL
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#define CONTROL_HV_HARDWARE_ERROR 0x0010000000000000ULL
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#define CONTROL_END_OF_BLOCK 0x0020000000000000ULL
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#define CONTROL_START_OF_BLOCK 0x0040000000000000ULL
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#define CONTROL_ENCRYPT 0x0080000000000000ULL
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#define CONTROL_OPCODE 0xff00000000000000ULL
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#define CONTROL_OPCODE_SHIFT 56
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#define OPCODE_INPLACE_BIT 0x80ULL
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#define OPCODE_SSL_KEYBLOCK 0x10ULL
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#define OPCODE_COPY 0x20ULL
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#define OPCODE_ENCRYPT 0x40ULL
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#define OPCODE_AUTH_MAC 0x41ULL
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#endif /* !(__ASSEMBLY__) */
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/* NCS v2.0 hypervisor interfaces */
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#define HV_NCS_QTYPE_MAU 0x01
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#define HV_NCS_QTYPE_CWQ 0x02
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/* ncs_qconf()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_NCS_QCONF
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* ARG0: Queue type (HV_NCS_QTYPE_{MAU,CWQ})
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* ARG1: Real address of queue, or handle for unconfigure
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* ARG2: Number of entries in queue, zero for unconfigure
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* RET0: status
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* RET1: queue handle
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*
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* Configure a queue in the stream processing unit.
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*
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* The real address given as the base must be 64-byte
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* aligned.
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*
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* The queue size can range from a minimum of 2 to a maximum
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* of 64. The queue size must be a power of two.
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*
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* To unconfigure a queue, specify a length of zero and place
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* the queue handle into ARG1.
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*
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* On configure success the hypervisor will set the FIRST, HEAD,
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* and TAIL registers to the address of the first entry in the
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* queue. The LAST register will be set to point to the last
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* entry in the queue.
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*/
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#define HV_FAST_NCS_QCONF 0x111
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/* ncs_qinfo()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_NCS_QINFO
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* ARG0: Queue handle
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* RET0: status
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* RET1: Queue type (HV_NCS_QTYPE_{MAU,CWQ})
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* RET2: Queue base address
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* RET3: Number of entries
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*/
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#define HV_FAST_NCS_QINFO 0x112
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/* ncs_gethead()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_NCS_GETHEAD
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* ARG0: Queue handle
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* RET0: status
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* RET1: queue head offset
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*/
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#define HV_FAST_NCS_GETHEAD 0x113
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/* ncs_gettail()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_NCS_GETTAIL
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* ARG0: Queue handle
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* RET0: status
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* RET1: queue tail offset
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*/
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#define HV_FAST_NCS_GETTAIL 0x114
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/* ncs_settail()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_NCS_SETTAIL
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* ARG0: Queue handle
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* ARG1: New tail offset
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* RET0: status
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*/
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#define HV_FAST_NCS_SETTAIL 0x115
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/* ncs_qhandle_to_devino()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_NCS_QHANDLE_TO_DEVINO
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* ARG0: Queue handle
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* RET0: status
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* RET1: devino
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*/
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#define HV_FAST_NCS_QHANDLE_TO_DEVINO 0x116
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/* ncs_sethead_marker()
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* TRAP: HV_FAST_TRAP
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* FUNCTION: HV_FAST_NCS_SETHEAD_MARKER
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* ARG0: Queue handle
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* ARG1: New head offset
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* RET0: status
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*/
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#define HV_FAST_NCS_SETHEAD_MARKER 0x117
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#ifndef __ASSEMBLY__
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extern unsigned long sun4v_ncs_qconf(unsigned long queue_type,
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unsigned long queue_ra,
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unsigned long num_entries,
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unsigned long *qhandle);
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extern unsigned long sun4v_ncs_qinfo(unsigned long qhandle,
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unsigned long *queue_type,
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unsigned long *queue_ra,
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unsigned long *num_entries);
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extern unsigned long sun4v_ncs_gethead(unsigned long qhandle,
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unsigned long *head);
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extern unsigned long sun4v_ncs_gettail(unsigned long qhandle,
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unsigned long *tail);
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extern unsigned long sun4v_ncs_settail(unsigned long qhandle,
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unsigned long tail);
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extern unsigned long sun4v_ncs_qhandle_to_devino(unsigned long qhandle,
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unsigned long *devino);
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extern unsigned long sun4v_ncs_sethead_marker(unsigned long qhandle,
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unsigned long head);
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#endif /* !(__ASSEMBLY__) */
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#endif /* _N2_CORE_H */
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