2064ba23e5
This patch adds support for txx9wdt driver to rbhma3100, rbhma4200 and rbhma4500 platform. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1001 lines
29 KiB
C
1001 lines
29 KiB
C
/*
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* Toshiba rbtx4927 specific setup
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* Copyright 2001-2002 MontaVista Software Inc.
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*
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* Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2000 RidgeRun, Inc.
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* Author: RidgeRun, Inc.
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* glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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* Copyright 2002 MontaVista Software Inc.
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* Author: Michael Pruznick, michael_pruznick@mvista.com
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*
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* Copyright (C) 2004 MontaVista Software Inc.
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* Author: Manish Lachwani, mlachwani@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
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* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <asm/bootinfo.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <asm/reboot.h>
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#include <asm/time.h>
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#include <asm/txx9tmr.h>
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#ifdef CONFIG_TOSHIBA_FPCIB0
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#include <asm/tx4927/smsc_fdc37m81x.h>
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#endif
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#include <asm/tx4927/toshiba_rbtx4927.h>
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#ifdef CONFIG_PCI
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#include <asm/tx4927/tx4927_pci.h>
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#endif
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#ifdef CONFIG_SERIAL_TXX9
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#include <linux/serial_core.h>
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#endif
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#undef TOSHIBA_RBTX4927_SETUP_DEBUG
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#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
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#define TOSHIBA_RBTX4927_SETUP_SETUP ( 1 << 4 )
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#define TOSHIBA_RBTX4927_SETUP_PCIBIOS ( 1 << 7 )
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#define TOSHIBA_RBTX4927_SETUP_PCI1 ( 1 << 8 )
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#define TOSHIBA_RBTX4927_SETUP_PCI2 ( 1 << 9 )
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#define TOSHIBA_RBTX4927_SETUP_ALL 0xffffffff
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#endif
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#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
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static const u32 toshiba_rbtx4927_setup_debug_flag =
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(TOSHIBA_RBTX4927_SETUP_SETUP |
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| TOSHIBA_RBTX4927_SETUP_PCIBIOS | TOSHIBA_RBTX4927_SETUP_PCI1 |
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TOSHIBA_RBTX4927_SETUP_PCI2);
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#endif
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#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
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#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag,str...) \
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if ( (toshiba_rbtx4927_setup_debug_flag) & (flag) ) \
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{ \
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char tmp[100]; \
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sprintf( tmp, str ); \
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printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
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}
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#else
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#define TOSHIBA_RBTX4927_SETUP_DPRINTK(flag, str...)
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#endif
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/* These functions are used for rebooting or halting the machine*/
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extern void toshiba_rbtx4927_restart(char *command);
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extern void toshiba_rbtx4927_halt(void);
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extern void toshiba_rbtx4927_power_off(void);
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int tx4927_using_backplane = 0;
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extern void toshiba_rbtx4927_irq_setup(void);
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char *prom_getcmdline(void);
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#ifdef CONFIG_PCI
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#undef TX4927_SUPPORT_COMMAND_IO
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#undef TX4927_SUPPORT_PCI_66
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int tx4927_cpu_clock = 100000000; /* 100MHz */
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unsigned long mips_pci_io_base;
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unsigned long mips_pci_io_size;
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unsigned long mips_pci_mem_base;
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unsigned long mips_pci_mem_size;
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/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
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unsigned long mips_pci_io_pciaddr = 0;
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unsigned long mips_memory_upper;
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static int tx4927_ccfg_toeon = 1;
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static int tx4927_pcic_trdyto = 0; /* default: disabled */
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unsigned long tx4927_ce_base[8];
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void tx4927_reset_pci_pcic(void);
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int tx4927_pci66 = 0; /* 0:auto */
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#endif
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char *toshiba_name = "";
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#ifdef CONFIG_PCI
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extern struct pci_controller tx4927_controller;
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static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
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int top_bus, int busnr, int devfn)
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{
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static struct pci_dev dev;
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static struct pci_bus bus;
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dev.sysdata = (void *)hose;
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dev.devfn = devfn;
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bus.number = busnr;
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bus.ops = hose->pci_ops;
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bus.parent = NULL;
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dev.bus = &bus;
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return &dev;
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}
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#define EARLY_PCI_OP(rw, size, type) \
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static int early_##rw##_config_##size(struct pci_controller *hose, \
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int top_bus, int bus, int devfn, int offset, type value) \
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{ \
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return pci_##rw##_config_##size( \
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fake_pci_dev(hose, top_bus, bus, devfn), \
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offset, value); \
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}
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EARLY_PCI_OP(read, byte, u8 *)
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EARLY_PCI_OP(read, dword, u32 *)
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EARLY_PCI_OP(write, byte, u8)
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EARLY_PCI_OP(write, dword, u32)
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static int __init tx4927_pcibios_init(void)
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{
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unsigned int id;
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u32 pci_devfn;
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int devfn_start = 0;
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int devfn_stop = 0xff;
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int busno = 0; /* One bus on the Toshiba */
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struct pci_controller *hose = &tx4927_controller;
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TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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"-\n");
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for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) {
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early_read_config_dword(hose, busno, busno, pci_devfn,
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PCI_VENDOR_ID, &id);
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if (id == 0xffffffff) {
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continue;
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}
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if (id == 0x94601055) {
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u8 v08_64;
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u32 v32_b0;
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u8 v08_e1;
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#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
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char *s = " sb/isa --";
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#endif
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
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s);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x64, &v08_64);
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early_read_config_dword(hose, busno, busno,
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pci_devfn, 0xb0, &v32_b0);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0xe1, &v08_e1);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s beg 0x64 = 0x%02x\n", s, v08_64);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s beg 0xb0 = 0x%02x\n", s, v32_b0);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s beg 0xe1 = 0x%02x\n", s, v08_e1);
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/* serial irq control */
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v08_64 = 0xd0;
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/* serial irq pin */
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v32_b0 |= 0x00010000;
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/* ide irq on isa14 */
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v08_e1 &= 0xf0;
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v08_e1 |= 0x0d;
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s mid 0x64 = 0x%02x\n", s, v08_64);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s mid 0xb0 = 0x%02x\n", s, v32_b0);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s mid 0xe1 = 0x%02x\n", s, v08_e1);
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early_write_config_byte(hose, busno, busno,
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pci_devfn, 0x64, v08_64);
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early_write_config_dword(hose, busno, busno,
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pci_devfn, 0xb0, v32_b0);
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early_write_config_byte(hose, busno, busno,
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pci_devfn, 0xe1, v08_e1);
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#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
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{
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x64,
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&v08_64);
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early_read_config_dword(hose, busno, busno,
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pci_devfn, 0xb0,
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&v32_b0);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0xe1,
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&v08_e1);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s end 0x64 = 0x%02x\n", s, v08_64);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s end 0xb0 = 0x%02x\n", s, v32_b0);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s end 0xe1 = 0x%02x\n", s, v08_e1);
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}
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#endif
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
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s);
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}
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if (id == 0x91301055) {
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u8 v08_04;
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u8 v08_09;
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u8 v08_41;
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u8 v08_43;
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u8 v08_5c;
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#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
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char *s = " sb/ide --";
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#endif
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s beg\n",
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s);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x04, &v08_04);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x09, &v08_09);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x41, &v08_41);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x43, &v08_43);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x5c, &v08_5c);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s beg 0x04 = 0x%02x\n", s, v08_04);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s beg 0x09 = 0x%02x\n", s, v08_09);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s beg 0x41 = 0x%02x\n", s, v08_41);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s beg 0x43 = 0x%02x\n", s, v08_43);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s beg 0x5c = 0x%02x\n", s, v08_5c);
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/* enable ide master/io */
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v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
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/* enable ide native mode */
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v08_09 |= 0x05;
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/* enable primary ide */
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v08_41 |= 0x80;
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/* enable secondary ide */
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v08_43 |= 0x80;
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/*
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* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
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*
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* This line of code is intended to provide the user with a work
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* around solution to the anomalies cited in SMSC's anomaly sheet
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* entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
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*
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* !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
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*/
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v08_5c |= 0x01;
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s mid 0x04 = 0x%02x\n", s, v08_04);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s mid 0x09 = 0x%02x\n", s, v08_09);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s mid 0x41 = 0x%02x\n", s, v08_41);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s mid 0x43 = 0x%02x\n", s, v08_43);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s mid 0x5c = 0x%02x\n", s, v08_5c);
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early_write_config_byte(hose, busno, busno,
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pci_devfn, 0x5c, v08_5c);
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early_write_config_byte(hose, busno, busno,
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pci_devfn, 0x04, v08_04);
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early_write_config_byte(hose, busno, busno,
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pci_devfn, 0x09, v08_09);
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early_write_config_byte(hose, busno, busno,
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pci_devfn, 0x41, v08_41);
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early_write_config_byte(hose, busno, busno,
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pci_devfn, 0x43, v08_43);
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#ifdef TOSHIBA_RBTX4927_SETUP_DEBUG
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{
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x04,
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&v08_04);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x09,
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&v08_09);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x41,
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&v08_41);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x43,
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&v08_43);
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early_read_config_byte(hose, busno, busno,
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pci_devfn, 0x5c,
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&v08_5c);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s end 0x04 = 0x%02x\n", s, v08_04);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s end 0x09 = 0x%02x\n", s, v08_09);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s end 0x41 = 0x%02x\n", s, v08_41);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s end 0x43 = 0x%02x\n", s, v08_43);
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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":%s end 0x5c = 0x%02x\n", s, v08_5c);
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}
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#endif
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TOSHIBA_RBTX4927_SETUP_DPRINTK
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(TOSHIBA_RBTX4927_SETUP_PCIBIOS, ":%s end\n",
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s);
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}
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}
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register_pci_controller(&tx4927_controller);
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TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCIBIOS,
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"+\n");
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return 0;
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}
|
|
|
|
arch_initcall(tx4927_pcibios_init);
|
|
|
|
extern struct resource pci_io_resource;
|
|
extern struct resource pci_mem_resource;
|
|
|
|
void __init tx4927_pci_setup(void)
|
|
{
|
|
static int called = 0;
|
|
extern unsigned int tx4927_get_mem_size(void);
|
|
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "-\n");
|
|
|
|
mips_memory_upper = tx4927_get_mem_size() << 20;
|
|
mips_memory_upper += KSEG0;
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
|
|
"0x%08lx=mips_memory_upper\n",
|
|
mips_memory_upper);
|
|
mips_pci_io_base = TX4927_PCIIO;
|
|
mips_pci_io_size = TX4927_PCIIO_SIZE;
|
|
mips_pci_mem_base = TX4927_PCIMEM;
|
|
mips_pci_mem_size = TX4927_PCIMEM_SIZE;
|
|
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
|
|
"0x%08lx=mips_pci_io_base\n",
|
|
mips_pci_io_base);
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
|
|
"0x%08lx=mips_pci_io_size\n",
|
|
mips_pci_io_size);
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
|
|
"0x%08lx=mips_pci_mem_base\n",
|
|
mips_pci_mem_base);
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
|
|
"0x%08lx=mips_pci_mem_size\n",
|
|
mips_pci_mem_size);
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
|
|
"0x%08lx=pci_io_resource.start\n",
|
|
pci_io_resource.start);
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
|
|
"0x%08lx=pci_io_resource.end\n",
|
|
pci_io_resource.end);
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
|
|
"0x%08lx=pci_mem_resource.start\n",
|
|
pci_mem_resource.start);
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
|
|
"0x%08lx=pci_mem_resource.end\n",
|
|
pci_mem_resource.end);
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
|
|
"0x%08lx=mips_io_port_base",
|
|
mips_io_port_base);
|
|
if (!called) {
|
|
printk
|
|
("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
|
|
toshiba_name,
|
|
(unsigned short) (tx4927_pcicptr->pciid >> 16),
|
|
(unsigned short) (tx4927_pcicptr->pciid & 0xffff),
|
|
(unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
|
|
(!(tx4927_ccfgptr->
|
|
ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
|
|
"Internal");
|
|
called = 1;
|
|
}
|
|
printk("%s PCIC --%s PCICLK:", toshiba_name,
|
|
(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
|
|
if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
|
|
int pciclk = 0;
|
|
if (mips_machtype == MACH_TOSHIBA_RBTX4937)
|
|
switch ((unsigned long) tx4927_ccfgptr->
|
|
ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
|
|
case TX4937_CCFG_PCIDIVMODE_4:
|
|
pciclk = tx4927_cpu_clock / 4;
|
|
break;
|
|
case TX4937_CCFG_PCIDIVMODE_4_5:
|
|
pciclk = tx4927_cpu_clock * 2 / 9;
|
|
break;
|
|
case TX4937_CCFG_PCIDIVMODE_5:
|
|
pciclk = tx4927_cpu_clock / 5;
|
|
break;
|
|
case TX4937_CCFG_PCIDIVMODE_5_5:
|
|
pciclk = tx4927_cpu_clock * 2 / 11;
|
|
break;
|
|
case TX4937_CCFG_PCIDIVMODE_8:
|
|
pciclk = tx4927_cpu_clock / 8;
|
|
break;
|
|
case TX4937_CCFG_PCIDIVMODE_9:
|
|
pciclk = tx4927_cpu_clock / 9;
|
|
break;
|
|
case TX4937_CCFG_PCIDIVMODE_10:
|
|
pciclk = tx4927_cpu_clock / 10;
|
|
break;
|
|
case TX4937_CCFG_PCIDIVMODE_11:
|
|
pciclk = tx4927_cpu_clock / 11;
|
|
break;
|
|
}
|
|
|
|
else
|
|
switch ((unsigned long) tx4927_ccfgptr->
|
|
ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
|
|
case TX4927_CCFG_PCIDIVMODE_2_5:
|
|
pciclk = tx4927_cpu_clock * 2 / 5;
|
|
break;
|
|
case TX4927_CCFG_PCIDIVMODE_3:
|
|
pciclk = tx4927_cpu_clock / 3;
|
|
break;
|
|
case TX4927_CCFG_PCIDIVMODE_5:
|
|
pciclk = tx4927_cpu_clock / 5;
|
|
break;
|
|
case TX4927_CCFG_PCIDIVMODE_6:
|
|
pciclk = tx4927_cpu_clock / 6;
|
|
break;
|
|
}
|
|
|
|
printk("Internal(%dMHz)", pciclk / 1000000);
|
|
} else {
|
|
int pciclk = 0;
|
|
int pciclk_setting = *tx4927_pci_clk_ptr;
|
|
switch (pciclk_setting & TX4927_PCI_CLK_MASK) {
|
|
case TX4927_PCI_CLK_33:
|
|
pciclk = 33333333;
|
|
break;
|
|
case TX4927_PCI_CLK_25:
|
|
pciclk = 25000000;
|
|
break;
|
|
case TX4927_PCI_CLK_66:
|
|
pciclk = 66666666;
|
|
break;
|
|
case TX4927_PCI_CLK_50:
|
|
pciclk = 50000000;
|
|
break;
|
|
}
|
|
printk("External(%dMHz)", pciclk / 1000000);
|
|
}
|
|
printk("\n");
|
|
|
|
|
|
|
|
/* GB->PCI mappings */
|
|
tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
|
|
tx4927_pcicptr->g2piogbase = mips_pci_io_base |
|
|
#ifdef __BIG_ENDIAN
|
|
TX4927_PCIC_G2PIOGBASE_ECHG
|
|
#else
|
|
TX4927_PCIC_G2PIOGBASE_BSDIS
|
|
#endif
|
|
;
|
|
|
|
tx4927_pcicptr->g2piopbase = 0;
|
|
|
|
tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
|
|
tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
|
|
#ifdef __BIG_ENDIAN
|
|
TX4927_PCIC_G2PMnGBASE_ECHG
|
|
#else
|
|
TX4927_PCIC_G2PMnGBASE_BSDIS
|
|
#endif
|
|
;
|
|
tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
|
|
|
|
tx4927_pcicptr->g2pmmask[1] = 0;
|
|
tx4927_pcicptr->g2pmgbase[1] = 0;
|
|
tx4927_pcicptr->g2pmpbase[1] = 0;
|
|
tx4927_pcicptr->g2pmmask[2] = 0;
|
|
tx4927_pcicptr->g2pmgbase[2] = 0;
|
|
tx4927_pcicptr->g2pmpbase[2] = 0;
|
|
|
|
|
|
/* PCI->GB mappings (I/O 256B) */
|
|
tx4927_pcicptr->p2giopbase = 0; /* 256B */
|
|
|
|
/* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
|
|
tx4927_pcicptr->p2gm0plbase = 0;
|
|
tx4927_pcicptr->p2gm0pubase = 0;
|
|
tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
|
|
#ifdef __BIG_ENDIAN
|
|
TX4927_PCIC_P2GMnGBASE_TECHG
|
|
#else
|
|
TX4927_PCIC_P2GMnGBASE_TBSDIS
|
|
#endif
|
|
;
|
|
|
|
/* PCI->GB mappings (MEM 16MB) -not used */
|
|
tx4927_pcicptr->p2gm1plbase = 0xffffffff;
|
|
tx4927_pcicptr->p2gm1pubase = 0xffffffff;
|
|
tx4927_pcicptr->p2gmgbase[1] = 0;
|
|
|
|
/* PCI->GB mappings (MEM 1MB) -not used */
|
|
tx4927_pcicptr->p2gm2pbase = 0xffffffff;
|
|
tx4927_pcicptr->p2gmgbase[2] = 0;
|
|
|
|
|
|
/* Enable Initiator Memory 0 Space, I/O Space, Config */
|
|
tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
|
|
tx4927_pcicptr->pciccfg |=
|
|
TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
|
|
TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
|
|
|
|
|
|
/* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
|
|
tx4927_pcicptr->pcicfg1 = 0;
|
|
|
|
if (tx4927_pcic_trdyto >= 0) {
|
|
tx4927_pcicptr->g2ptocnt &= ~0xff;
|
|
tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
|
|
}
|
|
|
|
/* Clear All Local Bus Status */
|
|
tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
|
|
/* Enable All Local Bus Interrupts */
|
|
tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
|
|
/* Clear All Initiator Status */
|
|
tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
|
|
/* Enable All Initiator Interrupts */
|
|
tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
|
|
/* Clear All PCI Status Error */
|
|
tx4927_pcicptr->pcistatus =
|
|
(tx4927_pcicptr->pcistatus & 0x0000ffff) |
|
|
(TX4927_PCIC_PCISTATUS_ALL << 16);
|
|
/* Enable All PCI Status Error Interrupts */
|
|
tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
|
|
|
|
/* PCIC Int => IRC IRQ16 */
|
|
tx4927_pcicptr->pcicfg2 =
|
|
(tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
|
|
|
|
if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
|
|
/* XXX */
|
|
} else {
|
|
/* Reset Bus Arbiter */
|
|
tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
|
|
/* Enable Bus Arbiter */
|
|
tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
|
|
}
|
|
|
|
tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
|
|
PCI_COMMAND_MEMORY |
|
|
PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
|
|
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2,
|
|
":pci setup complete:\n");
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI2, "+\n");
|
|
}
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
static void __noreturn wait_forever(void)
|
|
{
|
|
while (1)
|
|
if (cpu_wait)
|
|
(*cpu_wait)();
|
|
}
|
|
|
|
void toshiba_rbtx4927_restart(char *command)
|
|
{
|
|
printk(KERN_NOTICE "System Rebooting...\n");
|
|
|
|
/* enable the s/w reset register */
|
|
writeb(RBTX4927_SW_RESET_ENABLE_SET, RBTX4927_SW_RESET_ENABLE);
|
|
|
|
/* wait for enable to be seen */
|
|
while ((readb(RBTX4927_SW_RESET_ENABLE) &
|
|
RBTX4927_SW_RESET_ENABLE_SET) == 0x00);
|
|
|
|
/* do a s/w reset */
|
|
writeb(RBTX4927_SW_RESET_DO_SET, RBTX4927_SW_RESET_DO);
|
|
|
|
/* do something passive while waiting for reset */
|
|
local_irq_disable();
|
|
wait_forever();
|
|
/* no return */
|
|
}
|
|
|
|
|
|
void toshiba_rbtx4927_halt(void)
|
|
{
|
|
printk(KERN_NOTICE "System Halted\n");
|
|
local_irq_disable();
|
|
wait_forever();
|
|
/* no return */
|
|
}
|
|
|
|
void toshiba_rbtx4927_power_off(void)
|
|
{
|
|
toshiba_rbtx4927_halt();
|
|
/* no return */
|
|
}
|
|
|
|
void __init plat_mem_setup(void)
|
|
{
|
|
int i;
|
|
u32 cp0_config;
|
|
char *argptr;
|
|
|
|
printk("CPU is %s\n", toshiba_name);
|
|
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
"-\n");
|
|
|
|
/* f/w leaves this on at startup */
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
":Clearing STO_ERL.\n");
|
|
clear_c0_status(ST0_ERL);
|
|
|
|
/* enable caches -- HCP5 does this, pmon does not */
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
":Enabling TX49_CONF_IC,TX49_CONF_DC.\n");
|
|
cp0_config = read_c0_config();
|
|
cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
|
|
write_c0_config(cp0_config);
|
|
|
|
set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
":mips_io_port_base=0x%08lx\n",
|
|
mips_io_port_base);
|
|
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
":Resource\n");
|
|
ioport_resource.end = 0xffffffff;
|
|
iomem_resource.end = 0xffffffff;
|
|
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
":ResetRoutines\n");
|
|
_machine_restart = toshiba_rbtx4927_restart;
|
|
_machine_halt = toshiba_rbtx4927_halt;
|
|
pm_power_off = toshiba_rbtx4927_power_off;
|
|
|
|
for (i = 0; i < TX4927_NR_TMR; i++)
|
|
txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
/* PCIC */
|
|
/*
|
|
* ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
|
|
*
|
|
* For TX4927:
|
|
* PCIDIVMODE[12:11]'s initial value is given by S9[4:3] (ON:0, OFF:1).
|
|
* CPU 166MHz: PCI 66MHz : PCIDIVMODE: 00 (1/2.5)
|
|
* CPU 200MHz: PCI 66MHz : PCIDIVMODE: 01 (1/3)
|
|
* CPU 166MHz: PCI 33MHz : PCIDIVMODE: 10 (1/5)
|
|
* CPU 200MHz: PCI 33MHz : PCIDIVMODE: 11 (1/6)
|
|
* i.e. S9[3]: ON (83MHz), OFF (100MHz)
|
|
*
|
|
* For TX4937:
|
|
* PCIDIVMODE[12:11]'s initial value is given by S1[5:4] (ON:0, OFF:1)
|
|
* PCIDIVMODE[10] is 0.
|
|
* CPU 266MHz: PCI 33MHz : PCIDIVMODE: 000 (1/8)
|
|
* CPU 266MHz: PCI 66MHz : PCIDIVMODE: 001 (1/4)
|
|
* CPU 300MHz: PCI 33MHz : PCIDIVMODE: 010 (1/9)
|
|
* CPU 300MHz: PCI 66MHz : PCIDIVMODE: 011 (1/4.5)
|
|
* CPU 333MHz: PCI 33MHz : PCIDIVMODE: 100 (1/10)
|
|
* CPU 333MHz: PCI 66MHz : PCIDIVMODE: 101 (1/5)
|
|
*
|
|
*/
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
|
|
"ccfg is %lx, PCIDIVMODE is %x\n",
|
|
(unsigned long) tx4927_ccfgptr->ccfg,
|
|
(unsigned long) tx4927_ccfgptr->ccfg &
|
|
(mips_machtype == MACH_TOSHIBA_RBTX4937 ?
|
|
TX4937_CCFG_PCIDIVMODE_MASK :
|
|
TX4927_CCFG_PCIDIVMODE_MASK));
|
|
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_PCI1,
|
|
"PCI66 mode is %lx, PCI mode is %lx, pci arb is %lx\n",
|
|
(unsigned long) tx4927_ccfgptr->
|
|
ccfg & TX4927_CCFG_PCI66,
|
|
(unsigned long) tx4927_ccfgptr->
|
|
ccfg & TX4927_CCFG_PCIMIDE,
|
|
(unsigned long) tx4927_ccfgptr->
|
|
ccfg & TX4927_CCFG_PCIXARB);
|
|
|
|
if (mips_machtype == MACH_TOSHIBA_RBTX4937)
|
|
switch ((unsigned long)tx4927_ccfgptr->
|
|
ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
|
|
case TX4937_CCFG_PCIDIVMODE_8:
|
|
case TX4937_CCFG_PCIDIVMODE_4:
|
|
tx4927_cpu_clock = 266666666; /* 266MHz */
|
|
break;
|
|
case TX4937_CCFG_PCIDIVMODE_9:
|
|
case TX4937_CCFG_PCIDIVMODE_4_5:
|
|
tx4927_cpu_clock = 300000000; /* 300MHz */
|
|
break;
|
|
default:
|
|
tx4927_cpu_clock = 333333333; /* 333MHz */
|
|
}
|
|
else
|
|
switch ((unsigned long)tx4927_ccfgptr->
|
|
ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
|
|
case TX4927_CCFG_PCIDIVMODE_2_5:
|
|
case TX4927_CCFG_PCIDIVMODE_5:
|
|
tx4927_cpu_clock = 166666666; /* 166MHz */
|
|
break;
|
|
default:
|
|
tx4927_cpu_clock = 200000000; /* 200MHz */
|
|
}
|
|
|
|
/* CCFG */
|
|
/* do reset on watchdog */
|
|
tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR;
|
|
/* enable Timeout BusError */
|
|
if (tx4927_ccfg_toeon)
|
|
tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE;
|
|
|
|
tx4927_pci_setup();
|
|
if (tx4927_using_backplane == 1)
|
|
printk("backplane board IS installed\n");
|
|
else
|
|
printk("No Backplane \n");
|
|
|
|
/* this is on ISA bus behind PCI bus, so need PCI up first */
|
|
#ifdef CONFIG_TOSHIBA_FPCIB0
|
|
{
|
|
if (tx4927_using_backplane) {
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK
|
|
(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
":fpcibo=yes\n");
|
|
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK
|
|
(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
":smsc_fdc37m81x_init()\n");
|
|
smsc_fdc37m81x_init(0x3f0);
|
|
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK
|
|
(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
":smsc_fdc37m81x_config_beg()\n");
|
|
smsc_fdc37m81x_config_beg();
|
|
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK
|
|
(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
":smsc_fdc37m81x_config_set(KBD)\n");
|
|
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
|
|
SMSC_FDC37M81X_KBD);
|
|
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
|
|
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
|
|
smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
|
|
1);
|
|
|
|
smsc_fdc37m81x_config_end();
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK
|
|
(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
":smsc_fdc37m81x_config_end()\n");
|
|
} else {
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK
|
|
(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
":fpcibo=not_found\n");
|
|
}
|
|
}
|
|
#else
|
|
{
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK
|
|
(TOSHIBA_RBTX4927_SETUP_SETUP, ":fpcibo=no\n");
|
|
}
|
|
#endif
|
|
|
|
#endif /* CONFIG_PCI */
|
|
|
|
#ifdef CONFIG_SERIAL_TXX9
|
|
{
|
|
extern int early_serial_txx9_setup(struct uart_port *port);
|
|
struct uart_port req;
|
|
for(i = 0; i < 2; i++) {
|
|
memset(&req, 0, sizeof(req));
|
|
req.line = i;
|
|
req.iotype = UPIO_MEM;
|
|
req.membase = (char *)(0xff1ff300 + i * 0x100);
|
|
req.mapbase = 0xff1ff300 + i * 0x100;
|
|
req.irq = TX4927_IRQ_PIC_BEG + 8 + i;
|
|
req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
|
|
req.uartclk = 50000000;
|
|
early_serial_txx9_setup(&req);
|
|
}
|
|
}
|
|
#ifdef CONFIG_SERIAL_TXX9_CONSOLE
|
|
argptr = prom_getcmdline();
|
|
if (strstr(argptr, "console=") == NULL) {
|
|
strcat(argptr, " console=ttyS0,38400");
|
|
}
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef CONFIG_ROOT_NFS
|
|
argptr = prom_getcmdline();
|
|
if (strstr(argptr, "root=") == NULL) {
|
|
strcat(argptr, " root=/dev/nfs rw");
|
|
}
|
|
#endif
|
|
|
|
|
|
#ifdef CONFIG_IP_PNP
|
|
argptr = prom_getcmdline();
|
|
if (strstr(argptr, "ip=") == NULL) {
|
|
strcat(argptr, " ip=any");
|
|
}
|
|
#endif
|
|
|
|
|
|
TOSHIBA_RBTX4927_SETUP_DPRINTK(TOSHIBA_RBTX4927_SETUP_SETUP,
|
|
"+\n");
|
|
}
|
|
|
|
void __init plat_time_init(void)
|
|
{
|
|
mips_hpt_frequency = tx4927_cpu_clock / 2;
|
|
if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS)
|
|
txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
|
|
TXX9_IRQ_BASE + 17,
|
|
50000000);
|
|
}
|
|
|
|
static int __init toshiba_rbtx4927_rtc_init(void)
|
|
{
|
|
static struct resource __initdata res = {
|
|
.start = 0x1c010000,
|
|
.end = 0x1c010000 + 0x800 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
};
|
|
struct platform_device *dev =
|
|
platform_device_register_simple("rtc-ds1742", -1, &res, 1);
|
|
return IS_ERR(dev) ? PTR_ERR(dev) : 0;
|
|
}
|
|
device_initcall(toshiba_rbtx4927_rtc_init);
|
|
|
|
static int __init rbtx4927_ne_init(void)
|
|
{
|
|
static struct resource __initdata res[] = {
|
|
{
|
|
.start = RBTX4927_RTL_8019_BASE,
|
|
.end = RBTX4927_RTL_8019_BASE + 0x20 - 1,
|
|
.flags = IORESOURCE_IO,
|
|
}, {
|
|
.start = RBTX4927_RTL_8019_IRQ,
|
|
.flags = IORESOURCE_IRQ,
|
|
}
|
|
};
|
|
struct platform_device *dev =
|
|
platform_device_register_simple("ne", -1,
|
|
res, ARRAY_SIZE(res));
|
|
return IS_ERR(dev) ? PTR_ERR(dev) : 0;
|
|
}
|
|
device_initcall(rbtx4927_ne_init);
|
|
|
|
/* Watchdog support */
|
|
|
|
static int __init txx9_wdt_init(unsigned long base)
|
|
{
|
|
struct resource res = {
|
|
.start = base,
|
|
.end = base + 0x100 - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
};
|
|
struct platform_device *dev =
|
|
platform_device_register_simple("txx9wdt", -1, &res, 1);
|
|
return IS_ERR(dev) ? PTR_ERR(dev) : 0;
|
|
}
|
|
|
|
static int __init rbtx4927_wdt_init(void)
|
|
{
|
|
return txx9_wdt_init(TX4927_TMR_REG(2) & 0xfffffffffULL);
|
|
}
|
|
device_initcall(rbtx4927_wdt_init);
|
|
|
|
/* Minimum CLK support */
|
|
|
|
struct clk *clk_get(struct device *dev, const char *id)
|
|
{
|
|
if (!strcmp(id, "imbus_clk"))
|
|
return (struct clk *)50000000;
|
|
return ERR_PTR(-ENOENT);
|
|
}
|
|
EXPORT_SYMBOL(clk_get);
|
|
|
|
int clk_enable(struct clk *clk)
|
|
{
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL(clk_enable);
|
|
|
|
void clk_disable(struct clk *clk)
|
|
{
|
|
}
|
|
EXPORT_SYMBOL(clk_disable);
|
|
|
|
unsigned long clk_get_rate(struct clk *clk)
|
|
{
|
|
return (unsigned long)clk;
|
|
}
|
|
EXPORT_SYMBOL(clk_get_rate);
|
|
|
|
void clk_put(struct clk *clk)
|
|
{
|
|
}
|
|
EXPORT_SYMBOL(clk_put);
|