2f2a74e637
The MSM SOC's DMA controller contains several security domains. On the MSM7x00, only security domain 3 is accessible to our CPU. The 7x30, however, uses security domain 2. Fix up the register definition macros to select this appropriately, based on configured target. Signed-off-by: Daniel Walker <dwalker@codeaurora.org> Signed-off-by: David Brown <davidb@codeaurora.org> Signed-off-by: Gregory Bean <gbean@codeaurora.org> Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
167 lines
5.5 KiB
C
167 lines
5.5 KiB
C
/* linux/include/asm-arm/arch-msm/dma.h
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*
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* Copyright (C) 2007 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ASM_ARCH_MSM_DMA_H
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#include <linux/list.h>
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#include <mach/msm_iomap.h>
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struct msm_dmov_errdata {
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uint32_t flush[6];
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};
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struct msm_dmov_cmd {
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struct list_head list;
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unsigned int cmdptr;
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void (*complete_func)(struct msm_dmov_cmd *cmd,
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unsigned int result,
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struct msm_dmov_errdata *err);
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};
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void msm_dmov_enqueue_cmd(unsigned id, struct msm_dmov_cmd *cmd);
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void msm_dmov_stop_cmd(unsigned id, struct msm_dmov_cmd *cmd, int graceful);
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int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr);
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#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
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#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
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#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
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#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
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#if defined(CONFIG_ARCH_MSM7X30)
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#define DMOV_SD_AARM DMOV_SD2
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#else
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#define DMOV_SD_AARM DMOV_SD3
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#endif
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#define DMOV_CMD_PTR(ch) DMOV_SD_AARM(0x000, ch)
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#define DMOV_CMD_LIST (0 << 29) /* does not work */
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#define DMOV_CMD_PTR_LIST (1 << 29) /* works */
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#define DMOV_CMD_INPUT_CFG (2 << 29) /* untested */
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#define DMOV_CMD_OUTPUT_CFG (3 << 29) /* untested */
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#define DMOV_CMD_ADDR(addr) ((addr) >> 3)
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#define DMOV_RSLT(ch) DMOV_SD_AARM(0x040, ch)
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#define DMOV_RSLT_VALID (1 << 31) /* 0 == host has empties result fifo */
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#define DMOV_RSLT_ERROR (1 << 3)
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#define DMOV_RSLT_FLUSH (1 << 2)
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#define DMOV_RSLT_DONE (1 << 1) /* top pointer done */
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#define DMOV_RSLT_USER (1 << 0) /* command with FR force result */
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#define DMOV_FLUSH0(ch) DMOV_SD_AARM(0x080, ch)
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#define DMOV_FLUSH1(ch) DMOV_SD_AARM(0x0C0, ch)
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#define DMOV_FLUSH2(ch) DMOV_SD_AARM(0x100, ch)
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#define DMOV_FLUSH3(ch) DMOV_SD_AARM(0x140, ch)
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#define DMOV_FLUSH4(ch) DMOV_SD_AARM(0x180, ch)
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#define DMOV_FLUSH5(ch) DMOV_SD_AARM(0x1C0, ch)
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#define DMOV_STATUS(ch) DMOV_SD_AARM(0x200, ch)
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#define DMOV_STATUS_RSLT_COUNT(n) (((n) >> 29))
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#define DMOV_STATUS_CMD_COUNT(n) (((n) >> 27) & 3)
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#define DMOV_STATUS_RSLT_VALID (1 << 1)
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#define DMOV_STATUS_CMD_PTR_RDY (1 << 0)
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#define DMOV_ISR DMOV_SD_AARM(0x380, 0)
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#define DMOV_CONFIG(ch) DMOV_SD_AARM(0x300, ch)
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#define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
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#define DMOV_CONFIG_FORCE_FLUSH_RSLT (1 << 1)
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#define DMOV_CONFIG_IRQ_EN (1 << 0)
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/* channel assignments */
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#define DMOV_NAND_CHAN 7
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#define DMOV_NAND_CRCI_CMD 5
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#define DMOV_NAND_CRCI_DATA 4
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#define DMOV_SDC1_CHAN 8
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#define DMOV_SDC1_CRCI 6
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#define DMOV_SDC2_CHAN 8
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#define DMOV_SDC2_CRCI 7
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#define DMOV_TSIF_CHAN 10
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#define DMOV_TSIF_CRCI 10
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#define DMOV_USB_CHAN 11
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/* no client rate control ifc (eg, ram) */
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#define DMOV_NONE_CRCI 0
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/* If the CMD_PTR register has CMD_PTR_LIST selected, the data mover
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* is going to walk a list of 32bit pointers as described below. Each
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* pointer points to a *array* of dmov_s, etc structs. The last pointer
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* in the list is marked with CMD_PTR_LP. The last struct in each array
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* is marked with CMD_LC (see below).
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*/
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#define CMD_PTR_ADDR(addr) ((addr) >> 3)
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#define CMD_PTR_LP (1 << 31) /* last pointer */
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#define CMD_PTR_PT (3 << 29) /* ? */
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/* Single Item Mode */
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typedef struct {
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unsigned cmd;
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unsigned src;
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unsigned dst;
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unsigned len;
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} dmov_s;
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/* Scatter/Gather Mode */
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typedef struct {
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unsigned cmd;
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unsigned src_dscr;
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unsigned dst_dscr;
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unsigned _reserved;
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} dmov_sg;
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/* Box mode */
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typedef struct {
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uint32_t cmd;
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uint32_t src_row_addr;
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uint32_t dst_row_addr;
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uint32_t src_dst_len;
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uint32_t num_rows;
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uint32_t row_offset;
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} dmov_box;
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/* bits for the cmd field of the above structures */
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#define CMD_LC (1 << 31) /* last command */
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#define CMD_FR (1 << 22) /* force result -- does not work? */
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#define CMD_OCU (1 << 21) /* other channel unblock */
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#define CMD_OCB (1 << 20) /* other channel block */
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#define CMD_TCB (1 << 19) /* ? */
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#define CMD_DAH (1 << 18) /* destination address hold -- does not work?*/
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#define CMD_SAH (1 << 17) /* source address hold -- does not work? */
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#define CMD_MODE_SINGLE (0 << 0) /* dmov_s structure used */
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#define CMD_MODE_SG (1 << 0) /* untested */
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#define CMD_MODE_IND_SG (2 << 0) /* untested */
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#define CMD_MODE_BOX (3 << 0) /* untested */
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#define CMD_DST_SWAP_BYTES (1 << 14) /* exchange each byte n with byte n+1 */
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#define CMD_DST_SWAP_SHORTS (1 << 15) /* exchange each short n with short n+1 */
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#define CMD_DST_SWAP_WORDS (1 << 16) /* exchange each word n with word n+1 */
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#define CMD_SRC_SWAP_BYTES (1 << 11) /* exchange each byte n with byte n+1 */
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#define CMD_SRC_SWAP_SHORTS (1 << 12) /* exchange each short n with short n+1 */
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#define CMD_SRC_SWAP_WORDS (1 << 13) /* exchange each word n with word n+1 */
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#define CMD_DST_CRCI(n) (((n) & 15) << 7)
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#define CMD_SRC_CRCI(n) (((n) & 15) << 3)
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#endif
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