84bbc16c1f
This patch adds IRQ support for S5PV310. ARM GIC is installed in S5PV310 instead of VIC which is in every other CPUs in S5P series. Several irq combiners are used to resolve the lack of irq lines in current implementation. Signed-off-by: Changhwan Youn <chaos.youn@samsung.com> Signed-off-by: Hyuk Lee <hyuk1.lee@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
125 lines
3 KiB
C
125 lines
3 KiB
C
/* linux/arch/arm/mach-s5pv310/irq-combiner.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Based on arch/arm/common/gic.c
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*
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* IRQ COMBINER support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <asm/mach/irq.h>
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#define COMBINER_ENABLE_SET 0x0
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#define COMBINER_ENABLE_CLEAR 0x4
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#define COMBINER_INT_STATUS 0xC
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static DEFINE_SPINLOCK(irq_controller_lock);
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struct combiner_chip_data {
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unsigned int irq_offset;
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void __iomem *base;
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};
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static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
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static inline void __iomem *combiner_base(unsigned int irq)
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{
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struct combiner_chip_data *combiner_data = get_irq_chip_data(irq);
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return combiner_data->base;
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}
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static void combiner_mask_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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__raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR);
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}
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static void combiner_unmask_irq(unsigned int irq)
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{
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u32 mask = 1 << (irq % 32);
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__raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET);
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}
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static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct combiner_chip_data *chip_data = get_irq_data(irq);
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struct irq_chip *chip = get_irq_chip(irq);
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unsigned int cascade_irq, combiner_irq;
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unsigned long status;
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/* primary controller ack'ing */
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chip->ack(irq);
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spin_lock(&irq_controller_lock);
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status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
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spin_unlock(&irq_controller_lock);
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if (status == 0)
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goto out;
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for (combiner_irq = 0; combiner_irq < 32; combiner_irq++) {
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if (status & 0x1)
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break;
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status >>= 1;
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}
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cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
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if (unlikely(cascade_irq >= NR_IRQS))
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do_bad_IRQ(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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out:
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/* primary controller unmasking */
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chip->unmask(irq);
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}
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static struct irq_chip combiner_chip = {
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.name = "COMBINER",
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.mask = combiner_mask_irq,
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.unmask = combiner_unmask_irq,
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};
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void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
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{
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if (combiner_nr >= MAX_COMBINER_NR)
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BUG();
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if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0)
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BUG();
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set_irq_chained_handler(irq, combiner_handle_cascade_irq);
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}
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void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
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unsigned int irq_start)
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{
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unsigned int i;
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if (combiner_nr >= MAX_COMBINER_NR)
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BUG();
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combiner_data[combiner_nr].base = base;
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combiner_data[combiner_nr].irq_offset = irq_start;
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/* Disable all interrupts */
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__raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR);
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/* Setup the Linux IRQ subsystem */
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for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
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+ MAX_IRQ_IN_COMBINER; i++) {
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set_irq_chip(i, &combiner_chip);
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set_irq_chip_data(i, &combiner_data[combiner_nr]);
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set_irq_handler(i, handle_level_irq);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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}
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