180 lines
5 KiB
C
180 lines
5 KiB
C
/*
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* Copyright (C) 2000,2001,2004 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/percpu.h>
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#include <linux/spinlock.h>
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#include <asm/addrspace.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/sibyte/bcm1480_regs.h>
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#include <asm/sibyte/sb1250_regs.h>
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#include <asm/sibyte/bcm1480_int.h>
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#include <asm/sibyte/bcm1480_scd.h>
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#include <asm/sibyte/sb1250.h>
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#define IMR_IP2_VAL K_BCM1480_INT_MAP_I0
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#define IMR_IP3_VAL K_BCM1480_INT_MAP_I1
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#define IMR_IP4_VAL K_BCM1480_INT_MAP_I2
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/*
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* The general purpose timer ticks at 1MHz independent if
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* the rest of the system
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*/
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static void sibyte_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned int cpu = smp_processor_id();
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void __iomem *timer_cfg, *timer_init;
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timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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__raw_writeq(0, timer_cfg);
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__raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, timer_init);
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__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
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timer_cfg);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* Stop the timer until we actually program a shot */
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case CLOCK_EVT_MODE_SHUTDOWN:
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__raw_writeq(0, timer_cfg);
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break;
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case CLOCK_EVT_MODE_UNUSED: /* shuddup gcc */
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case CLOCK_EVT_MODE_RESUME:
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;
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}
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}
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static int sibyte_next_event(unsigned long delta, struct clock_event_device *cd)
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{
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unsigned int cpu = smp_processor_id();
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void __iomem *timer_init;
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unsigned int cnt;
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int res;
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timer_init = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT));
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cnt = __raw_readq(timer_init);
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cnt += delta;
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__raw_writeq(cnt, timer_init);
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res = ((long)(__raw_readq(timer_init) - cnt ) > 0) ? -ETIME : 0;
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return res;
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}
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static irqreturn_t sibyte_counter_handler(int irq, void *dev_id)
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{
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unsigned int cpu = smp_processor_id();
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struct clock_event_device *cd = dev_id;
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void __iomem *timer_cfg;
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timer_cfg = IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG));
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/* Reset the timer */
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__raw_writeq(M_SCD_TIMER_ENABLE | M_SCD_TIMER_MODE_CONTINUOUS,
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timer_cfg);
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cd->event_handler(cd);
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return IRQ_HANDLED;
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}
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static DEFINE_PER_CPU(struct clock_event_device, sibyte_hpt_clockevent);
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static DEFINE_PER_CPU(struct irqaction, sibyte_hpt_irqaction);
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static DEFINE_PER_CPU(char [18], sibyte_hpt_name);
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void __cpuinit sb1480_clockevent_init(void)
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{
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unsigned int cpu = smp_processor_id();
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unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
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struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
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struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
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unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
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BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
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sprintf(name, "bcm1480-counter-%d", cpu);
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cd->name = name;
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cd->features = CLOCK_EVT_FEAT_PERIODIC |
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CLOCK_EVT_FEAT_ONESHOT;
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clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
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cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
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cd->min_delta_ns = clockevent_delta2ns(1, cd);
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cd->rating = 200;
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cd->irq = irq;
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cd->cpumask = cpumask_of_cpu(cpu);
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cd->set_next_event = sibyte_next_event;
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cd->set_mode = sibyte_set_mode;
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clockevents_register_device(cd);
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bcm1480_mask_irq(cpu, irq);
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/*
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* Map timer interrupt to IP[4] of this cpu
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*/
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__raw_writeq(IMR_IP4_VAL,
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IOADDR(A_BCM1480_IMR_REGISTER(cpu,
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R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3)));
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bcm1480_unmask_irq(cpu, irq);
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action->handler = sibyte_counter_handler;
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action->flags = IRQF_DISABLED | IRQF_PERCPU;
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action->name = name;
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action->dev_id = cd;
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setup_irq(irq, action);
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}
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static cycle_t bcm1480_hpt_read(void)
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{
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return (cycle_t) __raw_readq(IOADDR(A_SCD_ZBBUS_CYCLE_COUNT));
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}
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struct clocksource bcm1480_clocksource = {
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.name = "zbbus-cycles",
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.rating = 200,
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.read = bcm1480_hpt_read,
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.mask = CLOCKSOURCE_MASK(64),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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void __init sb1480_clocksource_init(void)
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{
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struct clocksource *cs = &bcm1480_clocksource;
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unsigned int plldiv;
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unsigned long zbbus;
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plldiv = G_BCM1480_SYS_PLL_DIV(__raw_readq(IOADDR(A_SCD_SYSTEM_CFG)));
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zbbus = ((plldiv >> 1) * 50000000) + ((plldiv & 1) * 25000000);
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clocksource_set_clock(cs, zbbus);
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clocksource_register(cs);
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}
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void __init plat_time_init(void)
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{
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sb1480_clocksource_init();
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sb1480_clockevent_init();
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}
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