8a9e1b0f56
Issue: Current tsc based delay_calibration can result in significant errors in loops_per_jiffy count when the platform events like SMIs (System Management Interrupts that are non-maskable) are present. This could lead to potential kernel panic(). This issue is becoming more visible with 2.6 kernel (as default HZ is 1000) and on platforms with higher SMI handling latencies. During the boot time, SMIs are mostly used by BIOS (for things like legacy keyboard emulation). Description: The psuedocode for current delay calibration with tsc based delay looks like (0) Estimate a value for loops_per_jiffy (1) While (loops_per_jiffy estimate is accurate enough) (2) wait for jiffy transition (jiffy1) (3) Note down current tsc (tsc1) (4) loop until tsc becomes tsc1 + loops_per_jiffy (5) check whether jiffy changed since jiffy1 or not and refine loops_per_jiffy estimate Consider the following cases Case 1: If SMIs happen between (2) and (3) above, we can end up with a loops_per_jiffy value that is too low. This results in shorted delays and kernel can panic () during boot (Mostly at IOAPIC timer initialization timer_irq_works() as we don't have enough timer interrupts in a specified interval). Case 2: If SMIs happen between (3) and (4) above, then we can end up with a loops_per_jiffy value that is too high. And with current i386 code, too high lpj value (greater than 17M) can result in a overflow in delay.c:__const_udelay() again resulting in shorter delay and panic(). Solution: The patch below makes the calibration routine aware of asynchronous events like SMIs. We increase the delay calibration time and also identify any significant errors (greater than 12.5%) in the calibration and notify it to user. Patch below changes both i386 and x86-64 architectures to use this new and improved calibrate_delay_direct() routine. Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
75 lines
1.6 KiB
C
75 lines
1.6 KiB
C
#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <asm/timer.h>
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#ifdef CONFIG_HPET_TIMER
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/*
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* HPET memory read is slower than tsc reads, but is more dependable as it
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* always runs at constant frequency and reduces complexity due to
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* cpufreq. So, we prefer HPET timer to tsc based one. Also, we cannot use
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* timer_pit when HPET is active. So, we default to timer_tsc.
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*/
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#endif
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/* list of timers, ordered by preference, NULL terminated */
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static struct init_timer_opts* __initdata timers[] = {
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#ifdef CONFIG_X86_CYCLONE_TIMER
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&timer_cyclone_init,
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#endif
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#ifdef CONFIG_HPET_TIMER
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&timer_hpet_init,
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#endif
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#ifdef CONFIG_X86_PM_TIMER
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&timer_pmtmr_init,
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#endif
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&timer_tsc_init,
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&timer_pit_init,
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NULL,
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};
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static char clock_override[10] __initdata;
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static int __init clock_setup(char* str)
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{
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if (str)
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strlcpy(clock_override, str, sizeof(clock_override));
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return 1;
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}
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__setup("clock=", clock_setup);
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/* The chosen timesource has been found to be bad.
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* Fall back to a known good timesource (the PIT)
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*/
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void clock_fallback(void)
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{
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cur_timer = &timer_pit;
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}
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/* iterates through the list of timers, returning the first
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* one that initializes successfully.
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*/
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struct timer_opts* __init select_timer(void)
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{
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int i = 0;
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/* find most preferred working timer */
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while (timers[i]) {
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if (timers[i]->init)
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if (timers[i]->init(clock_override) == 0)
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return timers[i]->opts;
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++i;
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}
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panic("select_timer: Cannot find a suitable timer\n");
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return NULL;
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}
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int read_current_timer(unsigned long *timer_val)
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{
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if (cur_timer->read_timer) {
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*timer_val = cur_timer->read_timer();
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return 0;
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}
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return -1;
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}
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