1e924e2f1e
When CoreB wakes up, it needs to read variables that CoreA might have modified, and might be in CoreB's cache. So kill CoreB's cache before going to sleep so that when we wake up, we are in a coherent state. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
40 lines
881 B
C
40 lines
881 B
C
/*
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* Copyright 2007-2009 Analog Devices Inc.
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* Graff Yang <graf.yang@analog.com>
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/smp.h>
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#include <asm/blackfin.h>
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#include <asm/cacheflush.h>
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#include <mach/pll.h>
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int hotplug_coreb;
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void platform_cpu_die(void)
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{
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unsigned long iwr;
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hotplug_coreb = 1;
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/*
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* When CoreB wakes up, the code in _coreb_trampoline_start cannot
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* turn off the data cache. This causes the CoreB failed to boot.
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* As a workaround, we invalidate all the data cache before sleep.
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*/
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blackfin_invalidate_entire_dcache();
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/* disable core timer */
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bfin_write_TCNTL(0);
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/* clear ipi interrupt IRQ_SUPPLE_0 of CoreB */
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bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + 1)));
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SSYNC();
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/* set CoreB wakeup by ipi0, iwr will be discarded */
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bfin_iwr_set_sup0(&iwr, &iwr, &iwr);
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SSYNC();
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coreb_die();
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}
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