298476220d
Currently when making changes to control registers, we typically need some time for changes to take effect (8 nops, generally). However, for sh4a we simply need to do an icbi.. This is a simple patch for implementing a general purpose ctrl_barrier() which functions as a control register write barrier. There's some additional documentation in the patch itself, but it's pretty self explanatory. There were also some places where we were not doing the barrier, which didn't seem to have any adverse effects on legacy parts, but certainly did on sh4a. It's safer to have the barrier in place for legacy parts as well in these cases, though this does make flush_tlb_all() more expensive (by an order of 8 nops). We can ifdef around the flush_tlb_all() case for now if it's clear that all legacy parts won't have a problem with this. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
381 lines
8.3 KiB
C
381 lines
8.3 KiB
C
/* $Id: fault.c,v 1.14 2004/01/13 05:52:11 kkojima Exp $
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*
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* linux/arch/sh/mm/fault.c
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2003 Paul Mundt
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*
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* Based on linux/arch/i386/mm/fault.c:
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* Copyright (C) 1995 Linus Torvalds
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*/
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/pgalloc.h>
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#include <asm/mmu_context.h>
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#include <asm/cacheflush.h>
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#include <asm/kgdb.h>
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extern void die(const char *,struct pt_regs *,long);
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/*
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* This routine handles page faults. It determines the address,
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* and the problem, and then passes it off to one of the appropriate
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* routines.
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*/
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asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long writeaccess,
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unsigned long address)
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{
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struct task_struct *tsk;
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struct mm_struct *mm;
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struct vm_area_struct * vma;
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unsigned long page;
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#ifdef CONFIG_SH_KGDB
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if (kgdb_nofault && kgdb_bus_err_hook)
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kgdb_bus_err_hook();
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#endif
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tsk = current;
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mm = tsk->mm;
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/*
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* If we're in an interrupt or have no user
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* context, we must not take the fault..
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*/
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if (in_atomic() || !mm)
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goto no_context;
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down_read(&mm->mmap_sem);
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vma = find_vma(mm, address);
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if (!vma)
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goto bad_area;
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if (vma->vm_start <= address)
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goto good_area;
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if (!(vma->vm_flags & VM_GROWSDOWN))
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goto bad_area;
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if (expand_stack(vma, address))
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goto bad_area;
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/*
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* Ok, we have a good vm_area for this memory access, so
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* we can handle it..
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*/
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good_area:
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if (writeaccess) {
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if (!(vma->vm_flags & VM_WRITE))
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goto bad_area;
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} else {
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if (!(vma->vm_flags & (VM_READ | VM_EXEC)))
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goto bad_area;
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}
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/*
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* If for any reason at all we couldn't handle the fault,
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* make sure we exit gracefully rather than endlessly redo
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* the fault.
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*/
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survive:
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switch (handle_mm_fault(mm, vma, address, writeaccess)) {
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case VM_FAULT_MINOR:
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tsk->min_flt++;
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break;
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case VM_FAULT_MAJOR:
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tsk->maj_flt++;
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break;
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case VM_FAULT_SIGBUS:
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goto do_sigbus;
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case VM_FAULT_OOM:
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goto out_of_memory;
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default:
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BUG();
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}
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up_read(&mm->mmap_sem);
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return;
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/*
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* Something tried to access memory that isn't in our memory map..
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* Fix it, but check if it's kernel or user first..
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*/
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bad_area:
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up_read(&mm->mmap_sem);
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if (user_mode(regs)) {
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tsk->thread.address = address;
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tsk->thread.error_code = writeaccess;
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force_sig(SIGSEGV, tsk);
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return;
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}
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no_context:
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/* Are we prepared to handle this kernel fault? */
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if (fixup_exception(regs))
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return;
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/*
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* Oops. The kernel tried to access some bad page. We'll have to
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* terminate things with extreme prejudice.
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*
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*/
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if (address < PAGE_SIZE)
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printk(KERN_ALERT "Unable to handle kernel NULL pointer dereference");
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else
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printk(KERN_ALERT "Unable to handle kernel paging request");
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printk(" at virtual address %08lx\n", address);
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printk(KERN_ALERT "pc = %08lx\n", regs->pc);
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asm volatile("mov.l %1, %0"
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: "=r" (page)
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: "m" (__m(MMU_TTB)));
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if (page) {
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page = ((unsigned long *) page)[address >> 22];
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printk(KERN_ALERT "*pde = %08lx\n", page);
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if (page & _PAGE_PRESENT) {
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page &= PAGE_MASK;
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address &= 0x003ff000;
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page = ((unsigned long *) __va(page))[address >> PAGE_SHIFT];
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printk(KERN_ALERT "*pte = %08lx\n", page);
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}
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}
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die("Oops", regs, writeaccess);
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do_exit(SIGKILL);
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/*
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* We ran out of memory, or some other thing happened to us that made
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* us unable to handle the page fault gracefully.
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*/
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out_of_memory:
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up_read(&mm->mmap_sem);
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if (current->pid == 1) {
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yield();
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down_read(&mm->mmap_sem);
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goto survive;
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}
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printk("VM: killing process %s\n", tsk->comm);
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if (user_mode(regs))
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do_exit(SIGKILL);
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goto no_context;
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do_sigbus:
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up_read(&mm->mmap_sem);
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/*
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* Send a sigbus, regardless of whether we were in kernel
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* or user mode.
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*/
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tsk->thread.address = address;
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tsk->thread.error_code = writeaccess;
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tsk->thread.trap_no = 14;
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force_sig(SIGBUS, tsk);
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/* Kernel mode? Handle exceptions or die */
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if (!user_mode(regs))
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goto no_context;
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}
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/*
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* Called with interrupt disabled.
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*/
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asmlinkage int __do_page_fault(struct pt_regs *regs, unsigned long writeaccess,
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unsigned long address)
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{
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unsigned long addrmax = P4SEG;
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pgd_t *pgd;
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pmd_t *pmd;
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pte_t *pte;
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pte_t entry;
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struct mm_struct *mm;
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spinlock_t *ptl;
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int ret = 1;
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#ifdef CONFIG_SH_KGDB
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if (kgdb_nofault && kgdb_bus_err_hook)
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kgdb_bus_err_hook();
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#endif
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#ifdef CONFIG_SH_STORE_QUEUES
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addrmax = P4SEG_STORE_QUE + 0x04000000;
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#endif
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if (address >= P3SEG && address < addrmax) {
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pgd = pgd_offset_k(address);
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mm = NULL;
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} else if (address >= TASK_SIZE)
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return 1;
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else if (!(mm = current->mm))
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return 1;
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else
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pgd = pgd_offset(mm, address);
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pmd = pmd_offset(pgd, address);
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if (pmd_none_or_clear_bad(pmd))
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return 1;
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if (mm)
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pte = pte_offset_map_lock(mm, pmd, address, &ptl);
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else
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pte = pte_offset_kernel(pmd, address);
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entry = *pte;
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if (pte_none(entry) || pte_not_present(entry)
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|| (writeaccess && !pte_write(entry)))
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goto unlock;
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if (writeaccess)
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entry = pte_mkdirty(entry);
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entry = pte_mkyoung(entry);
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#ifdef CONFIG_CPU_SH4
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/*
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* ITLB is not affected by "ldtlb" instruction.
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* So, we need to flush the entry by ourselves.
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*/
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{
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unsigned long flags;
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local_irq_save(flags);
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__flush_tlb_page(get_asid(), address&PAGE_MASK);
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local_irq_restore(flags);
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}
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#endif
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set_pte(pte, entry);
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update_mmu_cache(NULL, address, entry);
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ret = 0;
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unlock:
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if (mm)
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pte_unmap_unlock(pte, ptl);
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return ret;
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}
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void flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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if (vma->vm_mm && vma->vm_mm->context != NO_CONTEXT) {
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unsigned long flags;
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unsigned long asid;
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unsigned long saved_asid = MMU_NO_ASID;
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asid = vma->vm_mm->context & MMU_CONTEXT_ASID_MASK;
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page &= PAGE_MASK;
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local_irq_save(flags);
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if (vma->vm_mm != current->mm) {
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saved_asid = get_asid();
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set_asid(asid);
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}
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__flush_tlb_page(asid, page);
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if (saved_asid != MMU_NO_ASID)
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set_asid(saved_asid);
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local_irq_restore(flags);
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}
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}
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void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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if (mm->context != NO_CONTEXT) {
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
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mm->context = NO_CONTEXT;
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if (mm == current->mm)
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activate_context(mm);
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} else {
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unsigned long asid = mm->context&MMU_CONTEXT_ASID_MASK;
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unsigned long saved_asid = MMU_NO_ASID;
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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if (mm != current->mm) {
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saved_asid = get_asid();
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set_asid(asid);
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}
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while (start < end) {
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__flush_tlb_page(asid, start);
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start += PAGE_SIZE;
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}
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if (saved_asid != MMU_NO_ASID)
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set_asid(saved_asid);
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}
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local_irq_restore(flags);
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}
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}
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void flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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if (size > (MMU_NTLB_ENTRIES/4)) { /* Too many TLB to flush */
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flush_tlb_all();
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} else {
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unsigned long asid = init_mm.context&MMU_CONTEXT_ASID_MASK;
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unsigned long saved_asid = get_asid();
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start &= PAGE_MASK;
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end += (PAGE_SIZE - 1);
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end &= PAGE_MASK;
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set_asid(asid);
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while (start < end) {
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__flush_tlb_page(asid, start);
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start += PAGE_SIZE;
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}
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set_asid(saved_asid);
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}
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local_irq_restore(flags);
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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/* Invalidate all TLB of this process. */
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/* Instead of invalidating each TLB, we get new MMU context. */
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if (mm->context != NO_CONTEXT) {
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unsigned long flags;
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local_irq_save(flags);
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mm->context = NO_CONTEXT;
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if (mm == current->mm)
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activate_context(mm);
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local_irq_restore(flags);
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}
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}
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void flush_tlb_all(void)
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{
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unsigned long flags, status;
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/*
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* Flush all the TLB.
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*
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* Write to the MMU control register's bit:
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* TF-bit for SH-3, TI-bit for SH-4.
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* It's same position, bit #2.
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*/
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local_irq_save(flags);
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status = ctrl_inl(MMUCR);
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status |= 0x04;
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ctrl_outl(status, MMUCR);
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ctrl_barrier();
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local_irq_restore(flags);
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}
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