177 lines
5.2 KiB
C
177 lines
5.2 KiB
C
/*
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* Copyright 2000 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/ioport.h>
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#include <linux/mm.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <asm/cpu.h>
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#include <asm/bootinfo.h>
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#include <asm/irq.h>
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#include <asm/mipsregs.h>
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#include <asm/reboot.h>
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#include <asm/pgtable.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-pb1x00/pb1000.h>
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void board_reset(void)
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{
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}
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void __init board_setup(void)
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{
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u32 pin_func, static_cfg0;
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u32 sys_freqctrl, sys_clksrc;
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u32 prid = read_c0_prid();
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// set AUX clock to 12MHz * 8 = 96 MHz
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au_writel(8, SYS_AUXPLL);
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au_writel(0, SYS_PINSTATERD);
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udelay(100);
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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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/* zero and disable FREQ2 */
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sys_freqctrl = au_readl(SYS_FREQCTRL0);
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sys_freqctrl &= ~0xFFF00000;
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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/* zero and disable USBH/USBD clocks */
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sys_clksrc = au_readl(SYS_CLKSRC);
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sys_clksrc &= ~0x00007FE0;
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au_writel(sys_clksrc, SYS_CLKSRC);
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sys_freqctrl = au_readl(SYS_FREQCTRL0);
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sys_freqctrl &= ~0xFFF00000;
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sys_clksrc = au_readl(SYS_CLKSRC);
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sys_clksrc &= ~0x00007FE0;
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switch (prid & 0x000000FF)
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{
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case 0x00: /* DA */
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case 0x01: /* HA */
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case 0x02: /* HB */
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/* CPU core freq to 48MHz to slow it way down... */
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au_writel(4, SYS_CPUPLL);
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/*
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* Setup 48MHz FREQ2 from CPUPLL for USB Host
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*/
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/* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
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sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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/* CPU core freq to 384MHz */
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au_writel(0x20, SYS_CPUPLL);
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printk("Au1000: 48MHz OHCI workaround enabled\n");
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break;
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default: /* HC and newer */
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// FREQ2 = aux/2 = 48 MHz
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sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
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au_writel(sys_freqctrl, SYS_FREQCTRL0);
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break;
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}
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/*
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* Route 48MHz FREQ2 into USB Host and/or Device
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*/
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#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
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sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
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#endif
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au_writel(sys_clksrc, SYS_CLKSRC);
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// configure pins GPIO[14:9] as GPIO
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pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
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// 2nd USB port is USB host
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pin_func |= 0x8000;
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au_writel(pin_func, SYS_PINFUNC);
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au_writel(0x2800, SYS_TRIOUTCLR);
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au_writel(0x0030, SYS_OUTPUTCLR);
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#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
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// make gpio 15 an input (for interrupt line)
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pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x100);
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// we don't need I2S, so make it available for GPIO[31:29]
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pin_func |= (1<<5);
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au_writel(pin_func, SYS_PINFUNC);
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au_writel(0x8000, SYS_TRIOUTCLR);
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static_cfg0 = au_readl(MEM_STCFG0) & (u32)(~0xc00);
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au_writel(static_cfg0, MEM_STCFG0);
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// configure RCE2* for LCD
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au_writel(0x00000004, MEM_STCFG2);
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// MEM_STTIME2
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au_writel(0x09000000, MEM_STTIME2);
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// Set 32-bit base address decoding for RCE2*
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au_writel(0x10003ff0, MEM_STADDR2);
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// PCI CPLD setup
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// expand CE0 to cover PCI
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au_writel(0x11803e40, MEM_STADDR1);
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// burst visibility on
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au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
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au_writel(0x83, MEM_STCFG1); // ewait enabled, flash timing
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au_writel(0x33030a10, MEM_STTIME1); // slower timing for FPGA
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/* setup the static bus controller */
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au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
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au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
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au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
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#ifdef CONFIG_PCI
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au_writel(0, PCI_BRIDGE_CONFIG); // set extend byte to 0
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au_writel(0, SDRAM_MBAR); // set mbar to 0
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au_writel(0x2, SDRAM_CMD); // enable memory accesses
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au_sync_delay(1);
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#endif
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/* Enable Au1000 BCLK switching - note: sed1356 must not use
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* its BCLK (Au1000 LCLK) for any timings */
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switch (prid & 0x000000FF)
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{
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case 0x00: /* DA */
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case 0x01: /* HA */
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case 0x02: /* HB */
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break;
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default: /* HC and newer */
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/* Enable sys bus clock divider when IDLE state or no bus
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activity. */
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au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
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break;
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}
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}
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