8531a35e5e
Rework of SMTC support to make it work with the new clock event system, allowing "tickless" operation, and to make it compatible with the use of the "wait_irqoff" idle loop. The new clocking scheme means that the previously optional IPI instant replay mechanism is now required, and has been made more robust. Signed-off-by: Kevin D. Kissell <kevink@paralogos.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
46 lines
1.4 KiB
C
46 lines
1.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Kevin D. Kissell
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*/
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/*
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* Definitions used for common event timer implementation
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* for MIPS 4K-type processors and their MIPS MT variants.
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* Avoids unsightly extern declarations in C files.
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*/
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#ifndef __ASM_CEVT_R4K_H
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#define __ASM_CEVT_R4K_H
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DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
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void mips_event_handler(struct clock_event_device *dev);
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int c0_compare_int_usable(void);
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void mips_set_clock_mode(enum clock_event_mode, struct clock_event_device *);
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irqreturn_t c0_compare_interrupt(int, void *);
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extern struct irqaction c0_compare_irqaction;
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extern int cp0_timer_irq_installed;
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/*
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* Possibly handle a performance counter interrupt.
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* Return true if the timer interrupt should not be checked
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*/
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static inline int handle_perf_irq(int r2)
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{
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/*
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* The performance counter overflow interrupt may be shared with the
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* timer interrupt (cp0_perfcount_irq < 0). If it is and a
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* performance counter has overflowed (perf_irq() == IRQ_HANDLED)
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* and we can't reliably determine if a counter interrupt has also
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* happened (!r2) then don't check for a timer interrupt.
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*/
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return (cp0_perfcount_irq < 0) &&
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perf_irq() == IRQ_HANDLED &&
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!r2;
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}
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#endif /* __ASM_CEVT_R4K_H */
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