cd0e00c106
memory-barriers.txt has been updated with the following requirement. "When using writel(), a prior wmb() is not needed to guarantee that the cache coherent memory writes have completed before writing to the MMIO region." Current writeX() and iowriteX() implementations on alpha are not satisfying this requirement as the barrier is after the register write. Move mb() in writeX() and iowriteX() functions to guarantee that HW observes memory changes before performing register operations. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Matt Turner <mattst88@gmail.com>
588 lines
14 KiB
C
588 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ALPHA_IO_H
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#define __ALPHA_IO_H
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#ifdef __KERNEL__
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <asm/compiler.h>
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#include <asm/pgtable.h>
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#include <asm/machvec.h>
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#include <asm/hwrpb.h>
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/* The generic header contains only prototypes. Including it ensures that
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the implementation we have here matches that interface. */
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#include <asm-generic/iomap.h>
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/* We don't use IO slowdowns on the Alpha, but.. */
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#define __SLOW_DOWN_IO do { } while (0)
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#define SLOW_DOWN_IO do { } while (0)
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/*
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* Virtual -> physical identity mapping starts at this offset
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*/
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#ifdef USE_48_BIT_KSEG
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#define IDENT_ADDR 0xffff800000000000UL
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#else
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#define IDENT_ADDR 0xfffffc0000000000UL
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#endif
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/*
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* We try to avoid hae updates (thus the cache), but when we
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* do need to update the hae, we need to do it atomically, so
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* that any interrupts wouldn't get confused with the hae
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* register not being up-to-date with respect to the hardware
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* value.
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*/
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extern inline void __set_hae(unsigned long new_hae)
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{
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unsigned long flags = swpipl(IPL_MAX);
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barrier();
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alpha_mv.hae_cache = new_hae;
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*alpha_mv.hae_register = new_hae;
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mb();
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/* Re-read to make sure it was written. */
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new_hae = *alpha_mv.hae_register;
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setipl(flags);
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barrier();
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}
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extern inline void set_hae(unsigned long new_hae)
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{
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if (new_hae != alpha_mv.hae_cache)
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__set_hae(new_hae);
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}
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/*
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* Change virtual addresses to physical addresses and vv.
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*/
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#ifdef USE_48_BIT_KSEG
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static inline unsigned long virt_to_phys(void *address)
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{
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return (unsigned long)address - IDENT_ADDR;
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}
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static inline void * phys_to_virt(unsigned long address)
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{
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return (void *) (address + IDENT_ADDR);
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}
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#else
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static inline unsigned long virt_to_phys(void *address)
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{
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unsigned long phys = (unsigned long)address;
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/* Sign-extend from bit 41. */
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phys <<= (64 - 41);
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phys = (long)phys >> (64 - 41);
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/* Crop to the physical address width of the processor. */
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phys &= (1ul << hwrpb->pa_bits) - 1;
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return phys;
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}
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static inline void * phys_to_virt(unsigned long address)
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{
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return (void *)(IDENT_ADDR + (address & ((1ul << 41) - 1)));
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}
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#endif
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#define page_to_phys(page) page_to_pa(page)
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static inline dma_addr_t __deprecated isa_page_to_bus(struct page *page)
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{
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return page_to_phys(page);
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}
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/* Maximum PIO space address supported? */
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#define IO_SPACE_LIMIT 0xffff
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/*
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* Change addresses as seen by the kernel (virtual) to addresses as
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* seen by a device (bus), and vice versa.
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*
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* Note that this only works for a limited range of kernel addresses,
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* and very well may not span all memory. Consider this interface
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* deprecated in favour of the DMA-mapping API.
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*/
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extern unsigned long __direct_map_base;
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extern unsigned long __direct_map_size;
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static inline unsigned long __deprecated virt_to_bus(void *address)
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{
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unsigned long phys = virt_to_phys(address);
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unsigned long bus = phys + __direct_map_base;
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return phys <= __direct_map_size ? bus : 0;
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}
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#define isa_virt_to_bus virt_to_bus
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static inline void * __deprecated bus_to_virt(unsigned long address)
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{
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void *virt;
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/* This check is a sanity check but also ensures that bus address 0
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maps to virtual address 0 which is useful to detect null pointers
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(the NCR driver is much simpler if NULL pointers are preserved). */
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address -= __direct_map_base;
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virt = phys_to_virt(address);
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return (long)address <= 0 ? NULL : virt;
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}
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#define isa_bus_to_virt bus_to_virt
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/*
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* There are different chipsets to interface the Alpha CPUs to the world.
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*/
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#define IO_CONCAT(a,b) _IO_CONCAT(a,b)
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#define _IO_CONCAT(a,b) a ## _ ## b
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#ifdef CONFIG_ALPHA_GENERIC
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/* In a generic kernel, we always go through the machine vector. */
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#define REMAP1(TYPE, NAME, QUAL) \
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static inline TYPE generic_##NAME(QUAL void __iomem *addr) \
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{ \
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return alpha_mv.mv_##NAME(addr); \
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}
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#define REMAP2(TYPE, NAME, QUAL) \
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static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr) \
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{ \
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alpha_mv.mv_##NAME(b, addr); \
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}
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REMAP1(unsigned int, ioread8, /**/)
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REMAP1(unsigned int, ioread16, /**/)
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REMAP1(unsigned int, ioread32, /**/)
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REMAP1(u8, readb, const volatile)
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REMAP1(u16, readw, const volatile)
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REMAP1(u32, readl, const volatile)
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REMAP1(u64, readq, const volatile)
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REMAP2(u8, iowrite8, /**/)
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REMAP2(u16, iowrite16, /**/)
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REMAP2(u32, iowrite32, /**/)
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REMAP2(u8, writeb, volatile)
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REMAP2(u16, writew, volatile)
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REMAP2(u32, writel, volatile)
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REMAP2(u64, writeq, volatile)
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#undef REMAP1
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#undef REMAP2
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extern inline void __iomem *generic_ioportmap(unsigned long a)
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{
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return alpha_mv.mv_ioportmap(a);
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}
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static inline void __iomem *generic_ioremap(unsigned long a, unsigned long s)
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{
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return alpha_mv.mv_ioremap(a, s);
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}
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static inline void generic_iounmap(volatile void __iomem *a)
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{
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return alpha_mv.mv_iounmap(a);
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}
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static inline int generic_is_ioaddr(unsigned long a)
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{
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return alpha_mv.mv_is_ioaddr(a);
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}
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static inline int generic_is_mmio(const volatile void __iomem *a)
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{
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return alpha_mv.mv_is_mmio(a);
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}
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#define __IO_PREFIX generic
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#define generic_trivial_rw_bw 0
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#define generic_trivial_rw_lq 0
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#define generic_trivial_io_bw 0
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#define generic_trivial_io_lq 0
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#define generic_trivial_iounmap 0
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#else
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#if defined(CONFIG_ALPHA_APECS)
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# include <asm/core_apecs.h>
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#elif defined(CONFIG_ALPHA_CIA)
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# include <asm/core_cia.h>
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#elif defined(CONFIG_ALPHA_IRONGATE)
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# include <asm/core_irongate.h>
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#elif defined(CONFIG_ALPHA_JENSEN)
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# include <asm/jensen.h>
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#elif defined(CONFIG_ALPHA_LCA)
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# include <asm/core_lca.h>
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#elif defined(CONFIG_ALPHA_MARVEL)
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# include <asm/core_marvel.h>
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#elif defined(CONFIG_ALPHA_MCPCIA)
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# include <asm/core_mcpcia.h>
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#elif defined(CONFIG_ALPHA_POLARIS)
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# include <asm/core_polaris.h>
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#elif defined(CONFIG_ALPHA_T2)
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# include <asm/core_t2.h>
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#elif defined(CONFIG_ALPHA_TSUNAMI)
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# include <asm/core_tsunami.h>
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#elif defined(CONFIG_ALPHA_TITAN)
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# include <asm/core_titan.h>
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#elif defined(CONFIG_ALPHA_WILDFIRE)
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# include <asm/core_wildfire.h>
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#else
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#error "What system is this?"
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#endif
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#endif /* GENERIC */
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/*
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* We always have external versions of these routines.
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*/
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extern u8 inb(unsigned long port);
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extern u16 inw(unsigned long port);
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extern u32 inl(unsigned long port);
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extern void outb(u8 b, unsigned long port);
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extern void outw(u16 b, unsigned long port);
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extern void outl(u32 b, unsigned long port);
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extern u8 readb(const volatile void __iomem *addr);
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extern u16 readw(const volatile void __iomem *addr);
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extern u32 readl(const volatile void __iomem *addr);
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extern u64 readq(const volatile void __iomem *addr);
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extern void writeb(u8 b, volatile void __iomem *addr);
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extern void writew(u16 b, volatile void __iomem *addr);
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extern void writel(u32 b, volatile void __iomem *addr);
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extern void writeq(u64 b, volatile void __iomem *addr);
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extern u8 __raw_readb(const volatile void __iomem *addr);
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extern u16 __raw_readw(const volatile void __iomem *addr);
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extern u32 __raw_readl(const volatile void __iomem *addr);
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extern u64 __raw_readq(const volatile void __iomem *addr);
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extern void __raw_writeb(u8 b, volatile void __iomem *addr);
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extern void __raw_writew(u16 b, volatile void __iomem *addr);
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extern void __raw_writel(u32 b, volatile void __iomem *addr);
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extern void __raw_writeq(u64 b, volatile void __iomem *addr);
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/*
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* Mapping from port numbers to __iomem space is pretty easy.
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*/
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/* These two have to be extern inline because of the extern prototype from
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<asm-generic/iomap.h>. It is not legal to mix "extern" and "static" for
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the same declaration. */
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extern inline void __iomem *ioport_map(unsigned long port, unsigned int size)
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{
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return IO_CONCAT(__IO_PREFIX,ioportmap) (port);
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}
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extern inline void ioport_unmap(void __iomem *addr)
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{
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}
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static inline void __iomem *ioremap(unsigned long port, unsigned long size)
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{
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return IO_CONCAT(__IO_PREFIX,ioremap) (port, size);
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}
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static inline void __iomem *__ioremap(unsigned long port, unsigned long size,
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unsigned long flags)
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{
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return ioremap(port, size);
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}
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static inline void __iomem * ioremap_nocache(unsigned long offset,
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unsigned long size)
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{
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return ioremap(offset, size);
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}
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#define ioremap_wc ioremap_nocache
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#define ioremap_uc ioremap_nocache
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static inline void iounmap(volatile void __iomem *addr)
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{
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IO_CONCAT(__IO_PREFIX,iounmap)(addr);
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}
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static inline int __is_ioaddr(unsigned long addr)
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{
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return IO_CONCAT(__IO_PREFIX,is_ioaddr)(addr);
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}
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#define __is_ioaddr(a) __is_ioaddr((unsigned long)(a))
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static inline int __is_mmio(const volatile void __iomem *addr)
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{
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return IO_CONCAT(__IO_PREFIX,is_mmio)(addr);
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}
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/*
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* If the actual I/O bits are sufficiently trivial, then expand inline.
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*/
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#if IO_CONCAT(__IO_PREFIX,trivial_io_bw)
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extern inline unsigned int ioread8(void __iomem *addr)
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{
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unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread8)(addr);
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mb();
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return ret;
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}
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extern inline unsigned int ioread16(void __iomem *addr)
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{
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unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread16)(addr);
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mb();
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return ret;
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}
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extern inline void iowrite8(u8 b, void __iomem *addr)
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{
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mb();
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IO_CONCAT(__IO_PREFIX, iowrite8)(b, addr);
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}
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extern inline void iowrite16(u16 b, void __iomem *addr)
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{
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mb();
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IO_CONCAT(__IO_PREFIX, iowrite16)(b, addr);
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}
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extern inline u8 inb(unsigned long port)
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{
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return ioread8(ioport_map(port, 1));
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}
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extern inline u16 inw(unsigned long port)
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{
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return ioread16(ioport_map(port, 2));
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}
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extern inline void outb(u8 b, unsigned long port)
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{
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iowrite8(b, ioport_map(port, 1));
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}
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extern inline void outw(u16 b, unsigned long port)
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{
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iowrite16(b, ioport_map(port, 2));
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}
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#endif
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#if IO_CONCAT(__IO_PREFIX,trivial_io_lq)
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extern inline unsigned int ioread32(void __iomem *addr)
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{
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unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread32)(addr);
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mb();
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return ret;
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}
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extern inline void iowrite32(u32 b, void __iomem *addr)
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{
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mb();
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IO_CONCAT(__IO_PREFIX, iowrite32)(b, addr);
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}
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extern inline u32 inl(unsigned long port)
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{
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return ioread32(ioport_map(port, 4));
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}
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extern inline void outl(u32 b, unsigned long port)
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{
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iowrite32(b, ioport_map(port, 4));
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}
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#endif
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#if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1
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extern inline u8 __raw_readb(const volatile void __iomem *addr)
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{
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return IO_CONCAT(__IO_PREFIX,readb)(addr);
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}
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extern inline u16 __raw_readw(const volatile void __iomem *addr)
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{
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return IO_CONCAT(__IO_PREFIX,readw)(addr);
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}
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extern inline void __raw_writeb(u8 b, volatile void __iomem *addr)
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{
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IO_CONCAT(__IO_PREFIX,writeb)(b, addr);
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}
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extern inline void __raw_writew(u16 b, volatile void __iomem *addr)
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{
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IO_CONCAT(__IO_PREFIX,writew)(b, addr);
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}
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extern inline u8 readb(const volatile void __iomem *addr)
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{
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u8 ret = __raw_readb(addr);
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mb();
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return ret;
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}
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extern inline u16 readw(const volatile void __iomem *addr)
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{
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u16 ret = __raw_readw(addr);
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mb();
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return ret;
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}
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extern inline void writeb(u8 b, volatile void __iomem *addr)
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{
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mb();
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__raw_writeb(b, addr);
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}
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extern inline void writew(u16 b, volatile void __iomem *addr)
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{
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mb();
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__raw_writew(b, addr);
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}
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#endif
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#if IO_CONCAT(__IO_PREFIX,trivial_rw_lq) == 1
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extern inline u32 __raw_readl(const volatile void __iomem *addr)
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{
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return IO_CONCAT(__IO_PREFIX,readl)(addr);
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}
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extern inline u64 __raw_readq(const volatile void __iomem *addr)
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{
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return IO_CONCAT(__IO_PREFIX,readq)(addr);
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}
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extern inline void __raw_writel(u32 b, volatile void __iomem *addr)
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{
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IO_CONCAT(__IO_PREFIX,writel)(b, addr);
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}
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extern inline void __raw_writeq(u64 b, volatile void __iomem *addr)
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{
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IO_CONCAT(__IO_PREFIX,writeq)(b, addr);
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}
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extern inline u32 readl(const volatile void __iomem *addr)
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{
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u32 ret = __raw_readl(addr);
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mb();
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return ret;
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}
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extern inline u64 readq(const volatile void __iomem *addr)
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{
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u64 ret = __raw_readq(addr);
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mb();
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return ret;
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}
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extern inline void writel(u32 b, volatile void __iomem *addr)
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{
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mb();
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__raw_writel(b, addr);
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}
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extern inline void writeq(u64 b, volatile void __iomem *addr)
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{
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mb();
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__raw_writeq(b, addr);
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}
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#endif
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#define ioread16be(p) be16_to_cpu(ioread16(p))
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#define ioread32be(p) be32_to_cpu(ioread32(p))
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#define iowrite16be(v,p) iowrite16(cpu_to_be16(v), (p))
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#define iowrite32be(v,p) iowrite32(cpu_to_be32(v), (p))
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#define inb_p inb
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#define inw_p inw
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#define inl_p inl
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#define outb_p outb
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#define outw_p outw
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#define outl_p outl
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#define readb_relaxed(addr) __raw_readb(addr)
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#define readw_relaxed(addr) __raw_readw(addr)
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#define readl_relaxed(addr) __raw_readl(addr)
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#define readq_relaxed(addr) __raw_readq(addr)
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#define writeb_relaxed(b, addr) __raw_writeb(b, addr)
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#define writew_relaxed(b, addr) __raw_writew(b, addr)
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#define writel_relaxed(b, addr) __raw_writel(b, addr)
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#define writeq_relaxed(b, addr) __raw_writeq(b, addr)
|
|
|
|
#define mmiowb()
|
|
|
|
/*
|
|
* String version of IO memory access ops:
|
|
*/
|
|
extern void memcpy_fromio(void *, const volatile void __iomem *, long);
|
|
extern void memcpy_toio(volatile void __iomem *, const void *, long);
|
|
extern void _memset_c_io(volatile void __iomem *, unsigned long, long);
|
|
|
|
static inline void memset_io(volatile void __iomem *addr, u8 c, long len)
|
|
{
|
|
_memset_c_io(addr, 0x0101010101010101UL * c, len);
|
|
}
|
|
|
|
#define __HAVE_ARCH_MEMSETW_IO
|
|
static inline void memsetw_io(volatile void __iomem *addr, u16 c, long len)
|
|
{
|
|
_memset_c_io(addr, 0x0001000100010001UL * c, len);
|
|
}
|
|
|
|
/*
|
|
* String versions of in/out ops:
|
|
*/
|
|
extern void insb (unsigned long port, void *dst, unsigned long count);
|
|
extern void insw (unsigned long port, void *dst, unsigned long count);
|
|
extern void insl (unsigned long port, void *dst, unsigned long count);
|
|
extern void outsb (unsigned long port, const void *src, unsigned long count);
|
|
extern void outsw (unsigned long port, const void *src, unsigned long count);
|
|
extern void outsl (unsigned long port, const void *src, unsigned long count);
|
|
|
|
/*
|
|
* The Alpha Jensen hardware for some rather strange reason puts
|
|
* the RTC clock at 0x170 instead of 0x70. Probably due to some
|
|
* misguided idea about using 0x70 for NMI stuff.
|
|
*
|
|
* These defines will override the defaults when doing RTC queries
|
|
*/
|
|
|
|
#ifdef CONFIG_ALPHA_GENERIC
|
|
# define RTC_PORT(x) ((x) + alpha_mv.rtc_port)
|
|
#else
|
|
# ifdef CONFIG_ALPHA_JENSEN
|
|
# define RTC_PORT(x) (0x170+(x))
|
|
# else
|
|
# define RTC_PORT(x) (0x70 + (x))
|
|
# endif
|
|
#endif
|
|
#define RTC_ALWAYS_BCD 0
|
|
|
|
/*
|
|
* Some mucking forons use if[n]def writeq to check if platform has it.
|
|
* It's a bloody bad idea and we probably want ARCH_HAS_WRITEQ for them
|
|
* to play with; for now just use cpp anti-recursion logics and make sure
|
|
* that damn thing is defined and expands to itself.
|
|
*/
|
|
|
|
#define writeq writeq
|
|
#define readq readq
|
|
|
|
/*
|
|
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
|
|
* access
|
|
*/
|
|
#define xlate_dev_mem_ptr(p) __va(p)
|
|
|
|
/*
|
|
* Convert a virtual cached pointer to an uncached pointer
|
|
*/
|
|
#define xlate_dev_kmem_ptr(p) p
|
|
|
|
#endif /* __KERNEL__ */
|
|
|
|
#endif /* __ALPHA_IO_H */
|