260a1fd26c
* define new CONFIG_ARCH_MX21 (this one is currently mutually exclusive to CONFIG_ARCH_MX27, but this might change) * splits one header file. Memory definitions, interrupt sources, DMA channels are split into common part, i.MX27 specific and i.MX21 specific. * guard access to UART5/UART6, which don't exist on i.MX21 Signed-off-by: Holger Schurig <hs4233@mail.mn-solutions.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
129 lines
4.4 KiB
C
129 lines
4.4 KiB
C
/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This contains i.MX27-specific hardware definitions. For those
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* hardware pieces that are common between i.MX21 and i.MX27, have a
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* look at mx2x.h.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_MXC_MX27_H__
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#define __ASM_ARCH_MXC_MX27_H__
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#ifndef __ASM_ARCH_MXC_HARDWARE_H__
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#error "Do not include directly."
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#endif
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/* IRAM */
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#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
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#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000)
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#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000)
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#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000)
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#define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000)
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#define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000)
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#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000)
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#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000)
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#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000)
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#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000)
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#define OTG_BASE_ADDR USBOTG_BASE_ADDR
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#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
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#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)
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#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000)
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#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000)
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#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000)
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#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000)
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#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000)
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/* ROM patch */
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#define ROMP_BASE_ADDR 0x10041000
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#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000)
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/* Memory regions and CS */
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#define SDRAM_BASE_ADDR 0xA0000000
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#define CSD1_BASE_ADDR 0xB0000000
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#define CS0_BASE_ADDR 0xC0000000
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#define CS1_BASE_ADDR 0xC8000000
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#define CS2_BASE_ADDR 0xD0000000
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#define CS3_BASE_ADDR 0xD2000000
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#define CS4_BASE_ADDR 0xD4000000
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#define CS5_BASE_ADDR 0xD6000000
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#define PCMCIA_MEM_BASE_ADDR 0xDC000000
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/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
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#define X_MEMC_BASE_ADDR 0xD8000000
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#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
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#define X_MEMC_SIZE SZ_1M
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#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
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#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
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#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
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#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
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#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
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/* fixed interrupt numbers */
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#define MXC_INT_CCM 63
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#define MXC_INT_IIM 62
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#define MXC_INT_SAHARA 59
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#define MXC_INT_SCC_SCM 58
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#define MXC_INT_SCC_SMN 57
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#define MXC_INT_USB3 56
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#define MXC_INT_USB2 55
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#define MXC_INT_USB1 54
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#define MXC_INT_VPU 53
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#define MXC_INT_FEC 50
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#define MXC_INT_UART5 49
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#define MXC_INT_UART6 48
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#define MXC_INT_ATA 30
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#define MXC_INT_SDHC3 9
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#define MXC_INT_SDHC 7
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#define MXC_INT_RTIC 5
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#define MXC_INT_GPT4 4
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#define MXC_INT_GPT5 3
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#define MXC_INT_GPT6 2
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#define MXC_INT_I2C2 1
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/* fixed DMA request numbers */
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#define DMA_REQ_NFC 37
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#define DMA_REQ_SDHC3 36
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#define DMA_REQ_UART6_RX 35
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#define DMA_REQ_UART6_TX 34
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#define DMA_REQ_UART5_RX 33
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#define DMA_REQ_UART5_TX 32
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#define DMA_REQ_ATA_RCV 29
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#define DMA_REQ_ATA_TX 28
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#define DMA_REQ_MSHC 4
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/* silicon revisions specific to i.MX27 */
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#define CHIP_REV_1_0 0x00
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#define CHIP_REV_2_0 0x01
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#ifndef __ASSEMBLY__
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extern int mx27_revision(void);
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#endif
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/* Mandatory defines used globally */
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/* this is an i.MX27 CPU */
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#define cpu_is_mx27() (1)
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/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
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#define ARCH_NR_GPIOS (192 + 16)
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#endif /* __ASM_ARCH_MXC_MX27_H__ */
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