365bff806e
Until not so long ago, there were system log messages pointing to inconsistent MTRR setup of the video frame buffer caused by the way vesafb and X worked. While vesafb was fixed meanwhile, I believe fixing it there only hides a shortcoming in the MTRR code itself, in that that code is not symmetric with respect to the ordering of attempts to set up two (or more) regions where one contains the other. In the current shape, it permits only setting up sub-regions of pre-exisiting ones. The patch below makes this symmetric. While working on that I noticed a few more inconsistencies in that code, namely - use of 'unsigned int' for sizes in many, but not all places (the patch is converting this to use 'unsigned long' everywhere, which specifically might be necessary for x86-64 once a processor supporting more than 44 physical address bits would become available) - the code to correct inconsistent settings during secondary processor startup tried (if necessary) to correct, among other things, the value in IA32_MTRR_DEF_TYPE, however the newly computed value would never get used (i.e. stored in the respective MSR) - the generic range validation code checked that the end of the to-be-added range would be above 1MB; the value checked should have been the start of the range - when contained regions are detected, previously this was allowed only when the old region was uncacheable; this can be symmetric (i.e. the new region can also be uncacheable) and even further as per Intel's documentation write-trough and write-back for either region is also compatible with the respective opposite in the other Signed-off-by: Jan Beulich <jbeulich@novell.com> Signed-off-by: Andi Kleen <ak@suse.de>
121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
#include <linux/init.h>
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#include <linux/mm.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include "mtrr.h"
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static void
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amd_get_mtrr(unsigned int reg, unsigned long *base,
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unsigned long *size, mtrr_type * type)
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{
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unsigned long low, high;
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rdmsr(MSR_K6_UWCCR, low, high);
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/* Upper dword is region 1, lower is region 0 */
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if (reg == 1)
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low = high;
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/* The base masks off on the right alignment */
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*base = (low & 0xFFFE0000) >> PAGE_SHIFT;
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*type = 0;
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if (low & 1)
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*type = MTRR_TYPE_UNCACHABLE;
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if (low & 2)
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*type = MTRR_TYPE_WRCOMB;
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if (!(low & 3)) {
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*size = 0;
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return;
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}
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/*
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* This needs a little explaining. The size is stored as an
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* inverted mask of bits of 128K granularity 15 bits long offset
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* 2 bits
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*
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* So to get a size we do invert the mask and add 1 to the lowest
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* mask bit (4 as its 2 bits in). This gives us a size we then shift
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* to turn into 128K blocks
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*
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* eg 111 1111 1111 1100 is 512K
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*
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* invert 000 0000 0000 0011
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* +1 000 0000 0000 0100
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* *128K ...
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*/
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low = (~low) & 0x1FFFC;
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*size = (low + 4) << (15 - PAGE_SHIFT);
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return;
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}
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static void amd_set_mtrr(unsigned int reg, unsigned long base,
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unsigned long size, mtrr_type type)
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/* [SUMMARY] Set variable MTRR register on the local CPU.
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<reg> The register to set.
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<base> The base address of the region.
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<size> The size of the region. If this is 0 the region is disabled.
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<type> The type of the region.
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<do_safe> If TRUE, do the change safely. If FALSE, safety measures should
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be done externally.
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[RETURNS] Nothing.
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*/
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{
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u32 regs[2];
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/*
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* Low is MTRR0 , High MTRR 1
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*/
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rdmsr(MSR_K6_UWCCR, regs[0], regs[1]);
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/*
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* Blank to disable
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*/
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if (size == 0)
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regs[reg] = 0;
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else
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/* Set the register to the base, the type (off by one) and an
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inverted bitmask of the size The size is the only odd
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bit. We are fed say 512K We invert this and we get 111 1111
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1111 1011 but if you subtract one and invert you get the
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desired 111 1111 1111 1100 mask
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But ~(x - 1) == ~x + 1 == -x. Two's complement rocks! */
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regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC)
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| (base << PAGE_SHIFT) | (type + 1);
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/*
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* The writeback rule is quite specific. See the manual. Its
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* disable local interrupts, write back the cache, set the mtrr
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*/
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wbinvd();
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wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
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}
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static int amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
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{
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/* Apply the K6 block alignment and size rules
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In order
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o Uncached or gathering only
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o 128K or bigger block
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o Power of 2 block
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o base suitably aligned to the power
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*/
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if (type > MTRR_TYPE_WRCOMB || size < (1 << (17 - PAGE_SHIFT))
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|| (size & ~(size - 1)) - size || (base & (size - 1)))
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return -EINVAL;
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return 0;
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}
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static struct mtrr_ops amd_mtrr_ops = {
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.vendor = X86_VENDOR_AMD,
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.set = amd_set_mtrr,
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.get = amd_get_mtrr,
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.get_free_region = generic_get_free_region,
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.validate_add_page = amd_validate_add_page,
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.have_wrcomb = positive_have_wrcomb,
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};
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int __init amd_init_mtrr(void)
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{
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set_mtrr_ops(&amd_mtrr_ops);
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return 0;
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}
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//arch_initcall(amd_mtrr_init);
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