24d3194a2c
VC channel configuration is programmed based on settings coming from the PMIC configuration. Currently, the VC channel to PMIC mapping is a simple one-to-one mapping. Whenever a VC channel parameter is configured (i2c slave addres, PMIC register address, on/ret/off command), the corresponding bits are enabled in the VC channel configuration register. If necessary, the programmability of channel configuration settings could be extended to board/PMIC files, however, because this patch changes the channel configuration to be programmed based on existing values from the PMIC settings, it may not be required. Also note that starting with OMAP4, where there are more than 2 channels, one channel is identified as the "default" channel. When any of the bits in the channel config for the other channels are zero, it means to use the default channel. The OMAP4 TRM (at least through NDA version Q) is wrong in describing which is the default channel. The default channel on OMAP4 is MPU, not CORE as decribed in the TRM. Signed-off-by: Kevin Hilman <khilman@ti.com>
65 lines
2 KiB
C
65 lines
2 KiB
C
/*
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* OMAP3 Voltage Controller (VC) data
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*
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* Copyright (C) 2007, 2010 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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* Lesly A M <x0080970@ti.com>
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* Thara Gopinath <thara@ti.com>
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*
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* Copyright (C) 2008, 2011 Nokia Corporation
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* Kalle Jokiniemi
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <plat/common.h>
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#include "prm-regbits-34xx.h"
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#include "voltage.h"
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#include "vc.h"
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/*
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* VC data common to 34xx/36xx chips
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* XXX This stuff presumably belongs in the vc3xxx.c or vc.c file.
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*/
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static struct omap_vc_common omap3_vc_common = {
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.smps_sa_reg = OMAP3_PRM_VC_SMPS_SA_OFFSET,
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.smps_volra_reg = OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET,
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.smps_cmdra_reg = OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET,
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.bypass_val_reg = OMAP3_PRM_VC_BYPASS_VAL_OFFSET,
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.data_shift = OMAP3430_DATA_SHIFT,
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.slaveaddr_shift = OMAP3430_SLAVEADDR_SHIFT,
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.regaddr_shift = OMAP3430_REGADDR_SHIFT,
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.valid = OMAP3430_VALID_MASK,
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.cmd_on_shift = OMAP3430_VC_CMD_ON_SHIFT,
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.cmd_on_mask = OMAP3430_VC_CMD_ON_MASK,
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.cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT,
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.cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT,
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.cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT,
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.cfg_channel_reg = OMAP3_PRM_VC_CH_CONF_OFFSET,
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};
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struct omap_vc_channel omap3_vc_mpu = {
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.common = &omap3_vc_common,
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.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_0_OFFSET,
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.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA0_MASK,
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.smps_volra_mask = OMAP3430_VOLRA0_MASK,
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.smps_cmdra_mask = OMAP3430_CMDRA0_MASK,
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.cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT,
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};
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struct omap_vc_channel omap3_vc_core = {
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.common = &omap3_vc_common,
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.cmdval_reg = OMAP3_PRM_VC_CMD_VAL_1_OFFSET,
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.smps_sa_mask = OMAP3430_PRM_VC_SMPS_SA_SA1_MASK,
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.smps_volra_mask = OMAP3430_VOLRA1_MASK,
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.smps_cmdra_mask = OMAP3430_CMDRA1_MASK,
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.cfg_channel_sa_shift = OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT,
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};
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