33081adf8b
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6: (365 commits) ALSA: hda - Disable sticky PCM stream assignment for AD codecs ALSA: usb - Creative USB X-Fi volume knob support ALSA: ca0106: Use card specific dac id for mute controls. ALSA: ca0106: Allow different sound cards to use different SPI channel mappings. ALSA: ca0106: Create a nice spot for mapping channels to dacs. ALSA: ca0106: Move enabling of front dac out of hardcoded setup sequence. ALSA: ca0106: Pull out dac powering routine into separate function. ALSA: ca0106 - add Sound Blaster 5.1vx info. ASoC: tlv320dac33: Use usleep_range for delays ALSA: usb-audio: add Novation Launchpad support ALSA: hda - Add workarounds for CT-IBG controllers ALSA: hda - Fix wrong TLV mute bit for STAC/IDT codecs ASoC: tpa6130a2: Error handling for broken chip ASoC: max98088: Staticise m98088_eq_band ASoC: soc-core: Fix codec->name memory leak ALSA: hda - Apply ideapad quirk to Acer laptops with Cxt5066 ALSA: hda - Add some workarounds for Creative IBG ALSA: hda - Fix wrong SPDIF NID assignment for CA0110 ALSA: hda - Fix codec rename rules for ALC662-compatible codecs ALSA: hda - Add alc_init_jacks() call to other codecs ...
357 lines
9.4 KiB
C
357 lines
9.4 KiB
C
/*
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* P1022DS board specific routines
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*
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* Authors: Travis Wheatley <travis.wheatley@freescale.com>
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* Dave Liu <daveliu@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This file is taken from the Freescale P1022DS BSP, with modifications:
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* 2) No AMP support
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* 3) No PCI endpoint support
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/pci.h>
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#include <linux/of_platform.h>
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#include <linux/memblock.h>
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#include <asm/div64.h>
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#include <asm/mpic.h>
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#include <asm/swiotlb.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <asm/fsl_guts.h>
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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/*
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* Board-specific initialization of the DIU. This code should probably be
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* executed when the DIU is opened, rather than in arch code, but the DIU
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* driver does not have a mechanism for this (yet).
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*
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* This is especially problematic on the P1022DS because the local bus (eLBC)
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* and the DIU video signals share the same pins, which means that enabling the
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* DIU will disable access to NOR flash.
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*/
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/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
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#define CLKDVDR_PXCKEN 0x80000000
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#define CLKDVDR_PXCKINV 0x10000000
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#define CLKDVDR_PXCKDLY 0x06000000
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#define CLKDVDR_PXCLK_MASK 0x00FF0000
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/* Some ngPIXIS register definitions */
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#define PX_BRDCFG1_DVIEN 0x80
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#define PX_BRDCFG1_DFPEN 0x40
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#define PX_BRDCFG1_BACKLIGHT 0x20
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#define PX_BRDCFG1_DDCEN 0x10
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/*
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* DIU Area Descriptor
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*
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* Note that we need to byte-swap the value before it's written to the AD
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* register. So even though the registers don't look like they're in the same
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* bit positions as they are on the MPC8610, the same value is written to the
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* AD register on the MPC8610 and on the P1022.
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*/
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#define AD_BYTE_F 0x10000000
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#define AD_ALPHA_C_MASK 0x0E000000
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#define AD_ALPHA_C_SHIFT 25
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#define AD_BLUE_C_MASK 0x01800000
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#define AD_BLUE_C_SHIFT 23
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#define AD_GREEN_C_MASK 0x00600000
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#define AD_GREEN_C_SHIFT 21
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#define AD_RED_C_MASK 0x00180000
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#define AD_RED_C_SHIFT 19
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#define AD_PALETTE 0x00040000
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#define AD_PIXEL_S_MASK 0x00030000
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#define AD_PIXEL_S_SHIFT 16
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#define AD_COMP_3_MASK 0x0000F000
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#define AD_COMP_3_SHIFT 12
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#define AD_COMP_2_MASK 0x00000F00
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#define AD_COMP_2_SHIFT 8
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#define AD_COMP_1_MASK 0x000000F0
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#define AD_COMP_1_SHIFT 4
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#define AD_COMP_0_MASK 0x0000000F
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#define AD_COMP_0_SHIFT 0
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#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
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cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
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(blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
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(red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
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(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
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(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
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/**
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* p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
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*
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* The Area Descriptor is a 32-bit value that determine which bits in each
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* pixel are to be used for each color.
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*/
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static unsigned int p1022ds_get_pixel_format(unsigned int bits_per_pixel,
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int monitor_port)
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{
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switch (bits_per_pixel) {
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case 32:
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/* 0x88883316 */
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return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
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case 24:
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/* 0x88082219 */
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return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
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case 16:
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/* 0x65053118 */
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return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
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default:
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pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
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return 0;
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}
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}
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/**
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* p1022ds_set_gamma_table: update the gamma table, if necessary
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*
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* On some boards, the gamma table for some ports may need to be modified.
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* This is not the case on the P1022DS, so we do nothing.
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*/
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static void p1022ds_set_gamma_table(int monitor_port, char *gamma_table_base)
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{
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}
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/**
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* p1022ds_set_monitor_port: switch the output to a different monitor port
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*
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*/
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static void p1022ds_set_monitor_port(int monitor_port)
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{
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struct device_node *pixis_node;
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u8 __iomem *brdcfg1;
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pixis_node = of_find_compatible_node(NULL, NULL, "fsl,p1022ds-pixis");
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if (!pixis_node) {
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pr_err("p1022ds: missing ngPIXIS node\n");
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return;
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}
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brdcfg1 = of_iomap(pixis_node, 0);
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if (!brdcfg1) {
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pr_err("p1022ds: could not map ngPIXIS registers\n");
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return;
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}
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brdcfg1 += 9; /* BRDCFG1 is at offset 9 in the ngPIXIS */
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switch (monitor_port) {
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case 0: /* DVI */
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/* Enable the DVI port, disable the DFP and the backlight */
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clrsetbits_8(brdcfg1, PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT,
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PX_BRDCFG1_DVIEN);
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break;
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case 1: /* Single link LVDS */
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/* Enable the DFP port, disable the DVI and the backlight */
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clrsetbits_8(brdcfg1, PX_BRDCFG1_DVIEN | PX_BRDCFG1_BACKLIGHT,
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PX_BRDCFG1_DFPEN);
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break;
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default:
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pr_err("p1022ds: unsupported monitor port %i\n", monitor_port);
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}
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}
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/**
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* p1022ds_set_pixel_clock: program the DIU's clock
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*
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* @pixclock: the wavelength, in picoseconds, of the clock
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*/
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void p1022ds_set_pixel_clock(unsigned int pixclock)
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{
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struct device_node *guts_np = NULL;
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struct ccsr_guts_85xx __iomem *guts;
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unsigned long freq;
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u64 temp;
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u32 pxclk;
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/* Map the global utilities registers. */
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guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
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if (!guts_np) {
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pr_err("p1022ds: missing global utilties device node\n");
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return;
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}
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guts = of_iomap(guts_np, 0);
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of_node_put(guts_np);
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if (!guts) {
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pr_err("p1022ds: could not map global utilties device\n");
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return;
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}
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/* Convert pixclock from a wavelength to a frequency */
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temp = 1000000000000ULL;
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do_div(temp, pixclock);
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freq = temp;
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/* pixclk is the ratio of the platform clock to the pixel clock */
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pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
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/* Disable the pixel clock, and set it to non-inverted and no delay */
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clrbits32(&guts->clkdvdr,
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CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
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/* Enable the clock and set the pxclk */
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setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
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}
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/**
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* p1022ds_show_monitor_port: show the current monitor
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*
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* This function returns a string indicating whether the current monitor is
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* set to DVI or LVDS.
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*/
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ssize_t p1022ds_show_monitor_port(int monitor_port, char *buf)
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{
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return sprintf(buf, "%c0 - DVI\n%c1 - Single link LVDS\n",
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monitor_port == 0 ? '*' : ' ', monitor_port == 1 ? '*' : ' ');
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}
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/**
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* p1022ds_set_sysfs_monitor_port: set the monitor port for sysfs
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*/
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int p1022ds_set_sysfs_monitor_port(int val)
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{
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return val < 2 ? val : 0;
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}
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#endif
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void __init p1022_ds_pic_init(void)
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{
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struct mpic *mpic;
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struct resource r;
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struct device_node *np;
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np = of_find_node_by_type(NULL, "open-pic");
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if (!np) {
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pr_err("Could not find open-pic node\n");
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return;
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}
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if (of_address_to_resource(np, 0, &r)) {
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pr_err("Failed to map mpic register space\n");
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of_node_put(np);
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return;
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}
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mpic = mpic_alloc(np, r.start,
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MPIC_PRIMARY | MPIC_WANTS_RESET |
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MPIC_BIG_ENDIAN | MPIC_BROKEN_FRR_NIRQS |
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MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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of_node_put(np);
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mpic_init(mpic);
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}
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#ifdef CONFIG_SMP
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void __init mpc85xx_smp_init(void);
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#endif
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/*
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* Setup the architecture
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*/
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static void __init p1022_ds_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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dma_addr_t max = 0xffffffff;
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if (ppc_md.progress)
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ppc_md.progress("p1022_ds_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
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struct resource rsrc;
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struct pci_controller *hose;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == 0x8000)
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fsl_add_bridge(np, 1);
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else
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fsl_add_bridge(np, 0);
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hose = pci_find_hose_for_OF_device(np);
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max = min(max, hose->dma_window_base_cur +
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hose->dma_window_size);
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}
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#endif
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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diu_ops.get_pixel_format = p1022ds_get_pixel_format;
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diu_ops.set_gamma_table = p1022ds_set_gamma_table;
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diu_ops.set_monitor_port = p1022ds_set_monitor_port;
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diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
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diu_ops.show_monitor_port = p1022ds_show_monitor_port;
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diu_ops.set_sysfs_monitor_port = p1022ds_set_sysfs_monitor_port;
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#endif
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#ifdef CONFIG_SMP
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mpc85xx_smp_init();
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#endif
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#ifdef CONFIG_SWIOTLB
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if (memblock_end_of_DRAM() > max) {
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ppc_swiotlb_enable = 1;
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set_pci_dma_ops(&swiotlb_dma_ops);
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ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
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}
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#endif
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pr_info("Freescale P1022 DS reference board\n");
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}
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static struct of_device_id __initdata p1022_ds_ids[] = {
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{ .type = "soc", },
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{ .compatible = "soc", },
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{ .compatible = "simple-bus", },
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{ .compatible = "gianfar", },
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/* So that the DMA channel nodes can be probed individually: */
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{ .compatible = "fsl,eloplus-dma", },
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{},
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};
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static int __init p1022_ds_publish_devices(void)
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{
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return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
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}
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machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
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machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init p1022_ds_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "fsl,p1022ds");
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}
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define_machine(p1022_ds) {
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.name = "P1022 DS",
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.probe = p1022_ds_probe,
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.setup_arch = p1022_ds_setup_arch,
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.init_IRQ = p1022_ds_pic_init,
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#ifdef CONFIG_PCI
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.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
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#endif
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.get_irq = mpic_get_irq,
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.restart = fsl_rstcr_restart,
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.calibrate_decr = generic_calibrate_decr,
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.progress = udbg_progress,
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};
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