f4ae17aa0f
Allow usage of scratch register for current pgd even when MIPS_PGD_C0_CONTEXT is not configured. MIPS_PGD_C0_CONTEXT is set for 64r2 platforms to indicate availability of Xcontext for saving cpuid, thus freeing Context to be used for saving PGD. This option was also tied to using a scratch register for storing PGD. This commit will allow usage of scratch register to store the current pgd if one can be allocated for the platform, even when MIPS_PGD_C0_CONTEXT is not set. The cpuid will be kept in the CP0 Context register in this case. The code to store the current pgd for the TLB miss handler is now generated in all cases. When scratch register is available, the PGD is also stored in the scratch register. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/5906/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
37 lines
870 B
ArmAsm
37 lines
870 B
ArmAsm
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Micro-assembler generated tlb handler functions.
|
|
*
|
|
* Copyright (C) 2013 Broadcom Corporation.
|
|
*
|
|
* Based on mm/page-funcs.c
|
|
* Copyright (C) 2012 MIPS Technologies, Inc.
|
|
* Copyright (C) 2012 Ralf Baechle <ralf@linux-mips.org>
|
|
*/
|
|
#include <asm/asm.h>
|
|
#include <asm/regdef.h>
|
|
|
|
#define FASTPATH_SIZE 128
|
|
|
|
LEAF(tlbmiss_handler_setup_pgd)
|
|
.space 16 * 4
|
|
END(tlbmiss_handler_setup_pgd)
|
|
EXPORT(tlbmiss_handler_setup_pgd_end)
|
|
|
|
LEAF(handle_tlbm)
|
|
.space FASTPATH_SIZE * 4
|
|
END(handle_tlbm)
|
|
EXPORT(handle_tlbm_end)
|
|
|
|
LEAF(handle_tlbs)
|
|
.space FASTPATH_SIZE * 4
|
|
END(handle_tlbs)
|
|
EXPORT(handle_tlbs_end)
|
|
|
|
LEAF(handle_tlbl)
|
|
.space FASTPATH_SIZE * 4
|
|
END(handle_tlbl)
|
|
EXPORT(handle_tlbl_end)
|