2f0384e5fc
* 'x86-amd-nb-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86, amd_nb: Enable GART support for AMD family 0x15 CPUs x86, amd: Use compute unit information to determine thread siblings x86, amd: Extract compute unit information for AMD CPUs x86, amd: Add support for CPUID topology extension of AMD CPUs x86, nmi: Support NMI watchdog on newer AMD CPU families x86, mtrr: Assume SYS_CFG[Tom2ForceMemTypeWB] exists on all future AMD CPUs x86, k8: Rename k8.[ch] to amd_nb.[ch] and CONFIG_K8_NB to CONFIG_AMD_NB x86, k8-gart: Decouple handling of garts and northbridges x86, cacheinfo: Fix dependency of AMD L3 CID x86, kvm: add new AMD SVM feature bits x86, cpu: Fix allowed CPUID bits for KVM guests x86, cpu: Update AMD CPUID feature bits x86, cpu: Fix renamed, not-yet-shipping AMD CPUID feature bit x86, AMD: Remove needless CPU family check (for L3 cache info) x86, tsc: Remove CPU frequency calibration on AMD
70 lines
1.9 KiB
C
70 lines
1.9 KiB
C
/*
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* Routines to indentify additional cpu features that are scattered in
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* cpuid space.
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*/
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#include <linux/cpu.h>
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#include <asm/pat.h>
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#include <asm/processor.h>
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#include <asm/apic.h>
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struct cpuid_bit {
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u16 feature;
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u8 reg;
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u8 bit;
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u32 level;
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u32 sub_leaf;
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};
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enum cpuid_regs {
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CR_EAX = 0,
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CR_ECX,
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CR_EDX,
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CR_EBX
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};
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void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
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{
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u32 max_level;
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u32 regs[4];
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const struct cpuid_bit *cb;
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static const struct cpuid_bit __cpuinitconst cpuid_bits[] = {
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{ X86_FEATURE_DTS, CR_EAX, 0, 0x00000006, 0 },
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{ X86_FEATURE_IDA, CR_EAX, 1, 0x00000006, 0 },
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{ X86_FEATURE_ARAT, CR_EAX, 2, 0x00000006, 0 },
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{ X86_FEATURE_PLN, CR_EAX, 4, 0x00000006, 0 },
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{ X86_FEATURE_PTS, CR_EAX, 6, 0x00000006, 0 },
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{ X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 },
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{ X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 },
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{ X86_FEATURE_XSAVEOPT, CR_EAX, 0, 0x0000000d, 1 },
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{ X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 },
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{ X86_FEATURE_NPT, CR_EDX, 0, 0x8000000a, 0 },
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{ X86_FEATURE_LBRV, CR_EDX, 1, 0x8000000a, 0 },
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{ X86_FEATURE_SVML, CR_EDX, 2, 0x8000000a, 0 },
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{ X86_FEATURE_NRIPS, CR_EDX, 3, 0x8000000a, 0 },
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{ X86_FEATURE_TSCRATEMSR, CR_EDX, 4, 0x8000000a, 0 },
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{ X86_FEATURE_VMCBCLEAN, CR_EDX, 5, 0x8000000a, 0 },
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{ X86_FEATURE_FLUSHBYASID, CR_EDX, 6, 0x8000000a, 0 },
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{ X86_FEATURE_DECODEASSISTS, CR_EDX, 7, 0x8000000a, 0 },
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{ X86_FEATURE_PAUSEFILTER, CR_EDX,10, 0x8000000a, 0 },
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{ X86_FEATURE_PFTHRESHOLD, CR_EDX,12, 0x8000000a, 0 },
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{ 0, 0, 0, 0, 0 }
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};
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for (cb = cpuid_bits; cb->feature; cb++) {
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/* Verify that the level is valid */
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max_level = cpuid_eax(cb->level & 0xffff0000);
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if (max_level < cb->level ||
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max_level > (cb->level | 0xffff))
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continue;
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cpuid_count(cb->level, cb->sub_leaf, ®s[CR_EAX],
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®s[CR_EBX], ®s[CR_ECX], ®s[CR_EDX]);
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if (regs[cb->reg] & (1 << cb->bit))
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set_cpu_cap(c, cb->feature);
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}
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}
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