4ef0652a74
With cpu_gdt_descr having been converted to per-CPU data, the old object (in head.S) no longer needs to reserve space for each CPU's instance. With cpu_gdt_table not being used for CPU 0 anymore, it doesn't seem to need page alignment (or if in fact there is a need for it to retain that alignment, the whole object should go into .data.page_align). Signed-off-by: Jan Beulich <jbeulich@novell.com> Acked-by: Zachary Amsden <zach@vmware.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
533 lines
13 KiB
ArmAsm
533 lines
13 KiB
ArmAsm
/*
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* linux/arch/i386/kernel/head.S -- the 32-bit startup code.
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*
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* Copyright (C) 1991, 1992 Linus Torvalds
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*
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* Enhanced CPU detection and feature setting code by Mike Jagdis
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* and Martin Mares, November 1997.
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*/
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.text
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#include <linux/config.h>
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#include <linux/threads.h>
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#include <linux/linkage.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/desc.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/asm-offsets.h>
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#include <asm/setup.h>
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/*
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* References to members of the new_cpu_data structure.
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*/
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#define X86 new_cpu_data+CPUINFO_x86
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#define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor
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#define X86_MODEL new_cpu_data+CPUINFO_x86_model
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#define X86_MASK new_cpu_data+CPUINFO_x86_mask
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#define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math
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#define X86_CPUID new_cpu_data+CPUINFO_cpuid_level
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#define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability
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#define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id
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/*
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* This is how much memory *in addition to the memory covered up to
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* and including _end* we need mapped initially. We need one bit for
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* each possible page, but only in low memory, which means
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* 2^32/4096/8 = 128K worst case (4G/4G split.)
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*
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* Modulo rounding, each megabyte assigned here requires a kilobyte of
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* memory, which is currently unreclaimed.
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*
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* This should be a multiple of a page.
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*/
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#define INIT_MAP_BEYOND_END (128*1024)
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/*
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* 32-bit kernel entrypoint; only used by the boot CPU. On entry,
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* %esi points to the real-mode code as a 32-bit pointer.
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* CS and DS must be 4 GB flat segments, but we don't depend on
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* any particular GDT layout, because we load our own as soon as we
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* can.
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*/
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ENTRY(startup_32)
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/*
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* Set segments to known values.
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*/
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cld
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lgdt boot_gdt_descr - __PAGE_OFFSET
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movl $(__BOOT_DS),%eax
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movl %eax,%ds
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movl %eax,%es
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movl %eax,%fs
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movl %eax,%gs
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/*
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* Clear BSS first so that there are no surprises...
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* No need to cld as DF is already clear from cld above...
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*/
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xorl %eax,%eax
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movl $__bss_start - __PAGE_OFFSET,%edi
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movl $__bss_stop - __PAGE_OFFSET,%ecx
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subl %edi,%ecx
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shrl $2,%ecx
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rep ; stosl
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/*
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* Copy bootup parameters out of the way.
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* Note: %esi still has the pointer to the real-mode data.
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* With the kexec as boot loader, parameter segment might be loaded beyond
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* kernel image and might not even be addressable by early boot page tables.
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* (kexec on panic case). Hence copy out the parameters before initializing
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* page tables.
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*/
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movl $(boot_params - __PAGE_OFFSET),%edi
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movl $(PARAM_SIZE/4),%ecx
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cld
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rep
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movsl
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movl boot_params - __PAGE_OFFSET + NEW_CL_POINTER,%esi
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andl %esi,%esi
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jnz 2f # New command line protocol
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cmpw $(OLD_CL_MAGIC),OLD_CL_MAGIC_ADDR
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jne 1f
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movzwl OLD_CL_OFFSET,%esi
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addl $(OLD_CL_BASE_ADDR),%esi
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2:
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movl $(saved_command_line - __PAGE_OFFSET),%edi
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movl $(COMMAND_LINE_SIZE/4),%ecx
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rep
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movsl
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1:
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/*
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* Initialize page tables. This creates a PDE and a set of page
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* tables, which are located immediately beyond _end. The variable
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* init_pg_tables_end is set up to point to the first "safe" location.
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* Mappings are created both at virtual address 0 (identity mapping)
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* and PAGE_OFFSET for up to _end+sizeof(page tables)+INIT_MAP_BEYOND_END.
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*
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* Warning: don't use %esi or the stack in this code. However, %esp
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* can be used as a GPR if you really need it...
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*/
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page_pde_offset = (__PAGE_OFFSET >> 20);
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movl $(pg0 - __PAGE_OFFSET), %edi
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movl $(swapper_pg_dir - __PAGE_OFFSET), %edx
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movl $0x007, %eax /* 0x007 = PRESENT+RW+USER */
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10:
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leal 0x007(%edi),%ecx /* Create PDE entry */
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movl %ecx,(%edx) /* Store identity PDE entry */
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movl %ecx,page_pde_offset(%edx) /* Store kernel PDE entry */
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addl $4,%edx
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movl $1024, %ecx
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11:
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stosl
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addl $0x1000,%eax
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loop 11b
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/* End condition: we must map up to and including INIT_MAP_BEYOND_END */
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/* bytes beyond the end of our own page tables; the +0x007 is the attribute bits */
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leal (INIT_MAP_BEYOND_END+0x007)(%edi),%ebp
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cmpl %ebp,%eax
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jb 10b
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movl %edi,(init_pg_tables_end - __PAGE_OFFSET)
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#ifdef CONFIG_SMP
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xorl %ebx,%ebx /* This is the boot CPU (BSP) */
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jmp 3f
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/*
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* Non-boot CPU entry point; entered from trampoline.S
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* We can't lgdt here, because lgdt itself uses a data segment, but
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* we know the trampoline has already loaded the boot_gdt_table GDT
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* for us.
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*/
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ENTRY(startup_32_smp)
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cld
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movl $(__BOOT_DS),%eax
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movl %eax,%ds
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movl %eax,%es
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movl %eax,%fs
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movl %eax,%gs
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/*
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* New page tables may be in 4Mbyte page mode and may
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* be using the global pages.
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*
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* NOTE! If we are on a 486 we may have no cr4 at all!
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* So we do not try to touch it unless we really have
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* some bits in it to set. This won't work if the BSP
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* implements cr4 but this AP does not -- very unlikely
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* but be warned! The same applies to the pse feature
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* if not equally supported. --macro
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*
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* NOTE! We have to correct for the fact that we're
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* not yet offset PAGE_OFFSET..
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*/
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#define cr4_bits mmu_cr4_features-__PAGE_OFFSET
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movl cr4_bits,%edx
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andl %edx,%edx
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jz 6f
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movl %cr4,%eax # Turn on paging options (PSE,PAE,..)
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orl %edx,%eax
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movl %eax,%cr4
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btl $5, %eax # check if PAE is enabled
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jnc 6f
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/* Check if extended functions are implemented */
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movl $0x80000000, %eax
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cpuid
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cmpl $0x80000000, %eax
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jbe 6f
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mov $0x80000001, %eax
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cpuid
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/* Execute Disable bit supported? */
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btl $20, %edx
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jnc 6f
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/* Setup EFER (Extended Feature Enable Register) */
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movl $0xc0000080, %ecx
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rdmsr
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btsl $11, %eax
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/* Make changes effective */
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wrmsr
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6:
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/* This is a secondary processor (AP) */
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xorl %ebx,%ebx
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incl %ebx
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3:
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#endif /* CONFIG_SMP */
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/*
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* Enable paging
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*/
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movl $swapper_pg_dir-__PAGE_OFFSET,%eax
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movl %eax,%cr3 /* set the page table pointer.. */
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movl %cr0,%eax
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orl $0x80000000,%eax
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movl %eax,%cr0 /* ..and set paging (PG) bit */
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ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */
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1:
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/* Set up the stack pointer */
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lss stack_start,%esp
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/*
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* Initialize eflags. Some BIOS's leave bits like NT set. This would
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* confuse the debugger if this code is traced.
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* XXX - best to initialize before switching to protected mode.
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*/
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pushl $0
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popfl
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#ifdef CONFIG_SMP
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andl %ebx,%ebx
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jz 1f /* Initial CPU cleans BSS */
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jmp checkCPUtype
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1:
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#endif /* CONFIG_SMP */
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/*
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* start system 32-bit setup. We need to re-do some of the things done
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* in 16-bit mode for the "real" operations.
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*/
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call setup_idt
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checkCPUtype:
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movl $-1,X86_CPUID # -1 for no CPUID initially
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/* check if it is 486 or 386. */
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/*
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* XXX - this does a lot of unnecessary setup. Alignment checks don't
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* apply at our cpl of 0 and the stack ought to be aligned already, and
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* we don't need to preserve eflags.
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*/
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movb $3,X86 # at least 386
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pushfl # push EFLAGS
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popl %eax # get EFLAGS
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movl %eax,%ecx # save original EFLAGS
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xorl $0x240000,%eax # flip AC and ID bits in EFLAGS
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pushl %eax # copy to EFLAGS
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popfl # set EFLAGS
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pushfl # get new EFLAGS
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popl %eax # put it in eax
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xorl %ecx,%eax # change in flags
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pushl %ecx # restore original EFLAGS
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popfl
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testl $0x40000,%eax # check if AC bit changed
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je is386
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movb $4,X86 # at least 486
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testl $0x200000,%eax # check if ID bit changed
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je is486
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/* get vendor info */
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xorl %eax,%eax # call CPUID with 0 -> return vendor ID
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cpuid
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movl %eax,X86_CPUID # save CPUID level
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movl %ebx,X86_VENDOR_ID # lo 4 chars
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movl %edx,X86_VENDOR_ID+4 # next 4 chars
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movl %ecx,X86_VENDOR_ID+8 # last 4 chars
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orl %eax,%eax # do we have processor info as well?
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je is486
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movl $1,%eax # Use the CPUID instruction to get CPU type
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cpuid
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movb %al,%cl # save reg for future use
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andb $0x0f,%ah # mask processor family
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movb %ah,X86
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andb $0xf0,%al # mask model
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shrb $4,%al
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movb %al,X86_MODEL
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andb $0x0f,%cl # mask mask revision
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movb %cl,X86_MASK
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movl %edx,X86_CAPABILITY
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is486: movl $0x50022,%ecx # set AM, WP, NE and MP
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jmp 2f
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is386: movl $2,%ecx # set MP
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2: movl %cr0,%eax
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andl $0x80000011,%eax # Save PG,PE,ET
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orl %ecx,%eax
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movl %eax,%cr0
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call check_x87
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lgdt cpu_gdt_descr
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lidt idt_descr
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ljmp $(__KERNEL_CS),$1f
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1: movl $(__KERNEL_DS),%eax # reload all the segment registers
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movl %eax,%ss # after changing gdt.
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movl $(__USER_DS),%eax # DS/ES contains default USER segment
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movl %eax,%ds
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movl %eax,%es
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xorl %eax,%eax # Clear FS/GS and LDT
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movl %eax,%fs
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movl %eax,%gs
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lldt %ax
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cld # gcc2 wants the direction flag cleared at all times
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#ifdef CONFIG_SMP
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movb ready, %cl
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movb $1, ready
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cmpb $0,%cl
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je 1f # the first CPU calls start_kernel
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# all other CPUs call initialize_secondary
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call initialize_secondary
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jmp L6
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1:
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#endif /* CONFIG_SMP */
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call start_kernel
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L6:
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jmp L6 # main should never return here, but
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# just in case, we know what happens.
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/*
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* We depend on ET to be correct. This checks for 287/387.
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*/
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check_x87:
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movb $0,X86_HARD_MATH
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clts
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fninit
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fstsw %ax
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cmpb $0,%al
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je 1f
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movl %cr0,%eax /* no coprocessor: have to set bits */
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xorl $4,%eax /* set EM */
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movl %eax,%cr0
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ret
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ALIGN
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1: movb $1,X86_HARD_MATH
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.byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */
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ret
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/*
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* setup_idt
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*
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* sets up a idt with 256 entries pointing to
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* ignore_int, interrupt gates. It doesn't actually load
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* idt - that can be done only after paging has been enabled
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* and the kernel moved to PAGE_OFFSET. Interrupts
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* are enabled elsewhere, when we can be relatively
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* sure everything is ok.
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*
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* Warning: %esi is live across this function.
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*/
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setup_idt:
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lea ignore_int,%edx
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movl $(__KERNEL_CS << 16),%eax
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movw %dx,%ax /* selector = 0x0010 = cs */
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movw $0x8E00,%dx /* interrupt gate - dpl=0, present */
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lea idt_table,%edi
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mov $256,%ecx
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rp_sidt:
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movl %eax,(%edi)
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movl %edx,4(%edi)
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addl $8,%edi
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dec %ecx
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jne rp_sidt
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ret
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/* This is the default interrupt "handler" :-) */
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ALIGN
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ignore_int:
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cld
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#ifdef CONFIG_PRINTK
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pushl %eax
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pushl %ecx
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pushl %edx
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pushl %es
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pushl %ds
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movl $(__KERNEL_DS),%eax
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movl %eax,%ds
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movl %eax,%es
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pushl 16(%esp)
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pushl 24(%esp)
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pushl 32(%esp)
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pushl 40(%esp)
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pushl $int_msg
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#ifdef CONFIG_EARLY_PRINTK
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call early_printk
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#else
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call printk
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#endif
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addl $(5*4),%esp
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popl %ds
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popl %es
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popl %edx
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popl %ecx
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popl %eax
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#endif
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iret
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/*
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* Real beginning of normal "text" segment
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*/
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ENTRY(stext)
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ENTRY(_stext)
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/*
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* BSS section
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*/
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.section ".bss.page_aligned","w"
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ENTRY(swapper_pg_dir)
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.fill 1024,4,0
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ENTRY(empty_zero_page)
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.fill 4096,1,0
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/*
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* This starts the data section.
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*/
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.data
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ENTRY(stack_start)
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.long init_thread_union+THREAD_SIZE
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.long __BOOT_DS
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ready: .byte 0
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int_msg:
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.asciz "Unknown interrupt or fault at EIP %p %p %p\n"
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/*
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* The IDT and GDT 'descriptors' are a strange 48-bit object
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* only used by the lidt and lgdt instructions. They are not
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* like usual segment descriptors - they consist of a 16-bit
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* segment size, and 32-bit linear address value:
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*/
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.globl boot_gdt_descr
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.globl idt_descr
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ALIGN
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# early boot GDT descriptor (must use 1:1 address mapping)
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.word 0 # 32 bit align gdt_desc.address
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boot_gdt_descr:
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.word __BOOT_DS+7
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.long boot_gdt_table - __PAGE_OFFSET
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.word 0 # 32-bit align idt_desc.address
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idt_descr:
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.word IDT_ENTRIES*8-1 # idt contains 256 entries
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.long idt_table
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# boot GDT descriptor (later on used by CPU#0):
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.word 0 # 32 bit align gdt_desc.address
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cpu_gdt_descr:
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.word GDT_ENTRIES*8-1
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.long cpu_gdt_table
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/*
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* The boot_gdt_table must mirror the equivalent in setup.S and is
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* used only for booting.
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*/
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.align L1_CACHE_BYTES
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ENTRY(boot_gdt_table)
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.fill GDT_ENTRY_BOOT_CS,8,0
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.quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */
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.quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */
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/*
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* The Global Descriptor Table contains 28 quadwords, per-CPU.
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*/
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.align L1_CACHE_BYTES
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ENTRY(cpu_gdt_table)
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.quad 0x0000000000000000 /* NULL descriptor */
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.quad 0x0000000000000000 /* 0x0b reserved */
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.quad 0x0000000000000000 /* 0x13 reserved */
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.quad 0x0000000000000000 /* 0x1b reserved */
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.quad 0x0000000000000000 /* 0x20 unused */
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.quad 0x0000000000000000 /* 0x28 unused */
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.quad 0x0000000000000000 /* 0x33 TLS entry 1 */
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.quad 0x0000000000000000 /* 0x3b TLS entry 2 */
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.quad 0x0000000000000000 /* 0x43 TLS entry 3 */
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.quad 0x0000000000000000 /* 0x4b reserved */
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.quad 0x0000000000000000 /* 0x53 reserved */
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.quad 0x0000000000000000 /* 0x5b reserved */
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.quad 0x00cf9a000000ffff /* 0x60 kernel 4GB code at 0x00000000 */
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.quad 0x00cf92000000ffff /* 0x68 kernel 4GB data at 0x00000000 */
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.quad 0x00cffa000000ffff /* 0x73 user 4GB code at 0x00000000 */
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.quad 0x00cff2000000ffff /* 0x7b user 4GB data at 0x00000000 */
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.quad 0x0000000000000000 /* 0x80 TSS descriptor */
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.quad 0x0000000000000000 /* 0x88 LDT descriptor */
|
|
|
|
/*
|
|
* Segments used for calling PnP BIOS have byte granularity.
|
|
* They code segments and data segments have fixed 64k limits,
|
|
* the transfer segment sizes are set at run time.
|
|
*/
|
|
.quad 0x00409a000000ffff /* 0x90 32-bit code */
|
|
.quad 0x00009a000000ffff /* 0x98 16-bit code */
|
|
.quad 0x000092000000ffff /* 0xa0 16-bit data */
|
|
.quad 0x0000920000000000 /* 0xa8 16-bit data */
|
|
.quad 0x0000920000000000 /* 0xb0 16-bit data */
|
|
|
|
/*
|
|
* The APM segments have byte granularity and their bases
|
|
* are set at run time. All have 64k limits.
|
|
*/
|
|
.quad 0x00409a000000ffff /* 0xb8 APM CS code */
|
|
.quad 0x00009a000000ffff /* 0xc0 APM CS 16 code (16 bit) */
|
|
.quad 0x004092000000ffff /* 0xc8 APM DS data */
|
|
|
|
.quad 0x0000920000000000 /* 0xd0 - ESPFIX 16-bit SS */
|
|
.quad 0x0000000000000000 /* 0xd8 - unused */
|
|
.quad 0x0000000000000000 /* 0xe0 - unused */
|
|
.quad 0x0000000000000000 /* 0xe8 - unused */
|
|
.quad 0x0000000000000000 /* 0xf0 - unused */
|
|
.quad 0x0000000000000000 /* 0xf8 - GDT entry 31: double-fault TSS */
|
|
|