3696a8a426
This patch provides core support for CM-X270 platform. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
224 lines
4.9 KiB
C
224 lines
4.9 KiB
C
/*
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* linux/include/asm-arm/arch-pxa/hardware.h
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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/*
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* We requires absolute addresses.
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*/
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#define PCIO_BASE 0
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/*
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* Workarounds for at least 2 errata so far require this.
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* The mapping is set in mach-pxa/generic.c.
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*/
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#define UNCACHED_PHYS_0 0xff000000
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#define UNCACHED_ADDR UNCACHED_PHYS_0
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/*
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* Intel PXA2xx internal register mapping:
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*
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* 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
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* 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
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* 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
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* 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
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* 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
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* 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
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* 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
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*
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* Note that not all PXA2xx chips implement all those addresses, and the
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* kernel only maps the minimum needed range of this mapping.
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*/
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#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
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#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
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#ifndef __ASSEMBLY__
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# define __REG(x) (*((volatile u32 *)io_p2v(x)))
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/* With indexed regs we don't want to feed the index through io_p2v()
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especially if it is a variable, otherwise horrible code will result. */
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# define __REG2(x,y) \
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(*(volatile u32 *)((u32)&__REG(x) + (y)))
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# define __PREG(x) (io_v2p((u32)&(x)))
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#else
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# define __REG(x) io_p2v(x)
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# define __PREG(x) io_v2p(x)
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#endif
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_PXA25x
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#define __cpu_is_pxa21x(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xf3f; \
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_id == 0x212; \
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})
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#define __cpu_is_pxa25x(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xfff; \
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_id == 0x2d0 || _id == 0x290; \
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})
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#else
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#define __cpu_is_pxa21x(id) (0)
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#define __cpu_is_pxa25x(id) (0)
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#endif
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#ifdef CONFIG_PXA27x
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#define __cpu_is_pxa27x(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xfff; \
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_id == 0x411; \
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})
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#else
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#define __cpu_is_pxa27x(id) (0)
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#endif
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#ifdef CONFIG_CPU_PXA300
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#define __cpu_is_pxa300(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xfff; \
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_id == 0x688; \
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})
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#else
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#define __cpu_is_pxa300(id) (0)
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#endif
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#ifdef CONFIG_CPU_PXA310
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#define __cpu_is_pxa310(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xfff; \
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_id == 0x689; \
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})
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#else
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#define __cpu_is_pxa310(id) (0)
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#endif
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#ifdef CONFIG_CPU_PXA320
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#define __cpu_is_pxa320(id) \
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({ \
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unsigned int _id = (id) >> 4 & 0xfff; \
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_id == 0x603 || _id == 0x682; \
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})
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#else
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#define __cpu_is_pxa320(id) (0)
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#endif
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#define cpu_is_pxa21x() \
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({ \
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unsigned int id = read_cpuid(CPUID_ID); \
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__cpu_is_pxa21x(id); \
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})
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#define cpu_is_pxa25x() \
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({ \
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unsigned int id = read_cpuid(CPUID_ID); \
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__cpu_is_pxa25x(id); \
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})
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#define cpu_is_pxa27x() \
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({ \
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unsigned int id = read_cpuid(CPUID_ID); \
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__cpu_is_pxa27x(id); \
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})
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#define cpu_is_pxa300() \
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({ \
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unsigned int id = read_cpuid(CPUID_ID); \
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__cpu_is_pxa300(id); \
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})
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#define cpu_is_pxa310() \
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({ \
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unsigned int id = read_cpuid(CPUID_ID); \
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__cpu_is_pxa310(id); \
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})
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#define cpu_is_pxa320() \
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({ \
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unsigned int id = read_cpuid(CPUID_ID); \
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__cpu_is_pxa320(id); \
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})
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/*
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* CPUID Core Generation Bit
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* <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x
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* == 0x3 for pxa300/pxa310/pxa320
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*/
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#define __cpu_is_pxa2xx(id) \
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({ \
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unsigned int _id = (id) >> 13 & 0x7; \
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_id <= 0x2; \
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})
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#define __cpu_is_pxa3xx(id) \
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({ \
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unsigned int _id = (id) >> 13 & 0x7; \
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_id == 0x3; \
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})
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#define cpu_is_pxa2xx() \
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({ \
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unsigned int id = read_cpuid(CPUID_ID); \
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__cpu_is_pxa2xx(id); \
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})
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#define cpu_is_pxa3xx() \
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({ \
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unsigned int id = read_cpuid(CPUID_ID); \
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__cpu_is_pxa3xx(id); \
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})
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/*
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* Handy routine to set GPIO alternate functions
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*/
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extern int pxa_gpio_mode( int gpio_mode );
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/*
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* Return GPIO level, nonzero means high, zero is low
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*/
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extern int pxa_gpio_get_value(unsigned gpio);
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/*
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* Set output GPIO level
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*/
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extern void pxa_gpio_set_value(unsigned gpio, int value);
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/*
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* Routine to enable or disable CKEN
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*/
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static inline void __deprecated pxa_set_cken(int clock, int enable)
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{
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extern void __pxa_set_cken(int clock, int enable);
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__pxa_set_cken(clock, enable);
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}
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/*
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* return current memory and LCD clock frequency in units of 10kHz
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*/
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extern unsigned int get_memclk_frequency_10khz(void);
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#endif
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#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
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#define PCIBIOS_MIN_IO 0
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#define PCIBIOS_MIN_MEM 0
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#define pcibios_assign_all_busses() 1
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#endif
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#endif /* _ASM_ARCH_HARDWARE_H */
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