8a95bc8dfe
Commit 46d026ac
("powerpc/85xx: consolidate of_platform_bus_probe calls")
replaced platform-specific of_device_id tables with a single function
that probes the most of the busses in 85xx device trees. If a specific
platform needed additional busses probed, then it could call
of_platform_bus_probe() again. Typically, the additional platform-specific
busses are children of existing busses that have already been probed.
of_platform_bus_probe() does not handle those child busses automatically.
Unfortunately, this doesn't actually work. The second (platform-specific)
call to of_platform_bus_probe() never finds any of the busses it's asked
to find.
To remedy this, the platform-specific of_device_id tables are eliminated,
and their entries are merged into mpc85xx_common_ids[], so that all busses
are probed at once.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
489 lines
13 KiB
C
489 lines
13 KiB
C
/*
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* P1022DS board specific routines
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*
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* Authors: Travis Wheatley <travis.wheatley@freescale.com>
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* Dave Liu <daveliu@freescale.com>
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* Timur Tabi <timur@freescale.com>
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This file is taken from the Freescale P1022DS BSP, with modifications:
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* 2) No AMP support
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* 3) No PCI endpoint support
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/pci.h>
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#include <linux/of_platform.h>
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#include <linux/memblock.h>
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#include <asm/div64.h>
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#include <asm/mpic.h>
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#include <asm/swiotlb.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/fsl_pci.h>
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#include <asm/udbg.h>
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#include <asm/fsl_guts.h>
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#include "smp.h"
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#include "mpc85xx.h"
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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#define PMUXCR_ELBCDIU_MASK 0xc0000000
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#define PMUXCR_ELBCDIU_NOR16 0x80000000
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#define PMUXCR_ELBCDIU_DIU 0x40000000
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/*
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* Board-specific initialization of the DIU. This code should probably be
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* executed when the DIU is opened, rather than in arch code, but the DIU
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* driver does not have a mechanism for this (yet).
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*
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* This is especially problematic on the P1022DS because the local bus (eLBC)
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* and the DIU video signals share the same pins, which means that enabling the
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* DIU will disable access to NOR flash.
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*/
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/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
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#define CLKDVDR_PXCKEN 0x80000000
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#define CLKDVDR_PXCKINV 0x10000000
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#define CLKDVDR_PXCKDLY 0x06000000
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#define CLKDVDR_PXCLK_MASK 0x00FF0000
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/* Some ngPIXIS register definitions */
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#define PX_CTL 3
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#define PX_BRDCFG0 8
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#define PX_BRDCFG1 9
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#define PX_BRDCFG0_ELBC_SPI_MASK 0xc0
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#define PX_BRDCFG0_ELBC_SPI_ELBC 0x00
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#define PX_BRDCFG0_ELBC_SPI_NULL 0xc0
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#define PX_BRDCFG0_ELBC_DIU 0x02
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#define PX_BRDCFG1_DVIEN 0x80
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#define PX_BRDCFG1_DFPEN 0x40
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#define PX_BRDCFG1_BACKLIGHT 0x20
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#define PX_BRDCFG1_DDCEN 0x10
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#define PX_CTL_ALTACC 0x80
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/*
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* DIU Area Descriptor
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*
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* Note that we need to byte-swap the value before it's written to the AD
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* register. So even though the registers don't look like they're in the same
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* bit positions as they are on the MPC8610, the same value is written to the
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* AD register on the MPC8610 and on the P1022.
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*/
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#define AD_BYTE_F 0x10000000
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#define AD_ALPHA_C_MASK 0x0E000000
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#define AD_ALPHA_C_SHIFT 25
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#define AD_BLUE_C_MASK 0x01800000
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#define AD_BLUE_C_SHIFT 23
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#define AD_GREEN_C_MASK 0x00600000
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#define AD_GREEN_C_SHIFT 21
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#define AD_RED_C_MASK 0x00180000
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#define AD_RED_C_SHIFT 19
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#define AD_PALETTE 0x00040000
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#define AD_PIXEL_S_MASK 0x00030000
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#define AD_PIXEL_S_SHIFT 16
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#define AD_COMP_3_MASK 0x0000F000
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#define AD_COMP_3_SHIFT 12
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#define AD_COMP_2_MASK 0x00000F00
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#define AD_COMP_2_SHIFT 8
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#define AD_COMP_1_MASK 0x000000F0
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#define AD_COMP_1_SHIFT 4
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#define AD_COMP_0_MASK 0x0000000F
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#define AD_COMP_0_SHIFT 0
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#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
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cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
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(blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
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(red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
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(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
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(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
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/**
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* p1022ds_get_pixel_format: return the Area Descriptor for a given pixel depth
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*
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* The Area Descriptor is a 32-bit value that determine which bits in each
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* pixel are to be used for each color.
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*/
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static u32 p1022ds_get_pixel_format(enum fsl_diu_monitor_port port,
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unsigned int bits_per_pixel)
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{
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switch (bits_per_pixel) {
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case 32:
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/* 0x88883316 */
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return MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8);
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case 24:
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/* 0x88082219 */
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return MAKE_AD(4, 0, 1, 2, 2, 0, 8, 8, 8);
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case 16:
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/* 0x65053118 */
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return MAKE_AD(4, 2, 1, 0, 1, 5, 6, 5, 0);
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default:
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pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
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return 0;
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}
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}
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/**
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* p1022ds_set_gamma_table: update the gamma table, if necessary
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*
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* On some boards, the gamma table for some ports may need to be modified.
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* This is not the case on the P1022DS, so we do nothing.
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*/
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static void p1022ds_set_gamma_table(enum fsl_diu_monitor_port port,
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char *gamma_table_base)
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{
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}
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/**
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* p1022ds_set_monitor_port: switch the output to a different monitor port
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*
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*/
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static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
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{
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struct device_node *guts_node;
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struct device_node *indirect_node = NULL;
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struct ccsr_guts __iomem *guts;
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u8 __iomem *lbc_lcs0_ba = NULL;
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u8 __iomem *lbc_lcs1_ba = NULL;
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u8 b;
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/* Map the global utilities registers. */
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guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
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if (!guts_node) {
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pr_err("p1022ds: missing global utilties device node\n");
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return;
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}
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guts = of_iomap(guts_node, 0);
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if (!guts) {
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pr_err("p1022ds: could not map global utilties device\n");
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goto exit;
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}
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indirect_node = of_find_compatible_node(NULL, NULL,
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"fsl,p1022ds-indirect-pixis");
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if (!indirect_node) {
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pr_err("p1022ds: missing pixis indirect mode node\n");
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goto exit;
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}
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lbc_lcs0_ba = of_iomap(indirect_node, 0);
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if (!lbc_lcs0_ba) {
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pr_err("p1022ds: could not map localbus chip select 0\n");
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goto exit;
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}
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lbc_lcs1_ba = of_iomap(indirect_node, 1);
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if (!lbc_lcs1_ba) {
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pr_err("p1022ds: could not map localbus chip select 1\n");
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goto exit;
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}
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/* Make sure we're in indirect mode first. */
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if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
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PMUXCR_ELBCDIU_DIU) {
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struct device_node *pixis_node;
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void __iomem *pixis;
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pixis_node =
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of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
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if (!pixis_node) {
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pr_err("p1022ds: missing pixis node\n");
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goto exit;
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}
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pixis = of_iomap(pixis_node, 0);
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of_node_put(pixis_node);
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if (!pixis) {
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pr_err("p1022ds: could not map pixis registers\n");
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goto exit;
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}
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/* Enable indirect PIXIS mode. */
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setbits8(pixis + PX_CTL, PX_CTL_ALTACC);
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iounmap(pixis);
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/* Switch the board mux to the DIU */
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out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */
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b = in_8(lbc_lcs1_ba);
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b |= PX_BRDCFG0_ELBC_DIU;
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out_8(lbc_lcs1_ba, b);
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/* Set the chip mux to DIU mode. */
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clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
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PMUXCR_ELBCDIU_DIU);
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in_be32(&guts->pmuxcr);
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}
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switch (port) {
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case FSL_DIU_PORT_DVI:
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/* Enable the DVI port, disable the DFP and the backlight */
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out_8(lbc_lcs0_ba, PX_BRDCFG1);
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b = in_8(lbc_lcs1_ba);
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b &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
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b |= PX_BRDCFG1_DVIEN;
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out_8(lbc_lcs1_ba, b);
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break;
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case FSL_DIU_PORT_LVDS:
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/*
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* LVDS also needs backlight enabled, otherwise the display
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* will be blank.
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*/
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/* Enable the DFP port, disable the DVI and the backlight */
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out_8(lbc_lcs0_ba, PX_BRDCFG1);
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b = in_8(lbc_lcs1_ba);
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b &= ~PX_BRDCFG1_DVIEN;
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b |= PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT;
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out_8(lbc_lcs1_ba, b);
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break;
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default:
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pr_err("p1022ds: unsupported monitor port %i\n", port);
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}
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exit:
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if (lbc_lcs1_ba)
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iounmap(lbc_lcs1_ba);
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if (lbc_lcs0_ba)
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iounmap(lbc_lcs0_ba);
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if (guts)
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iounmap(guts);
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of_node_put(indirect_node);
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of_node_put(guts_node);
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}
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/**
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* p1022ds_set_pixel_clock: program the DIU's clock
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*
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* @pixclock: the wavelength, in picoseconds, of the clock
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*/
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void p1022ds_set_pixel_clock(unsigned int pixclock)
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{
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struct device_node *guts_np = NULL;
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struct ccsr_guts __iomem *guts;
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unsigned long freq;
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u64 temp;
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u32 pxclk;
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/* Map the global utilities registers. */
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guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
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if (!guts_np) {
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pr_err("p1022ds: missing global utilties device node\n");
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return;
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}
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guts = of_iomap(guts_np, 0);
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of_node_put(guts_np);
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if (!guts) {
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pr_err("p1022ds: could not map global utilties device\n");
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return;
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}
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/* Convert pixclock from a wavelength to a frequency */
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temp = 1000000000000ULL;
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do_div(temp, pixclock);
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freq = temp;
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/*
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* 'pxclk' is the ratio of the platform clock to the pixel clock.
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* This number is programmed into the CLKDVDR register, and the valid
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* range of values is 2-255.
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*/
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pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
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pxclk = clamp_t(u32, pxclk, 2, 255);
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/* Disable the pixel clock, and set it to non-inverted and no delay */
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clrbits32(&guts->clkdvdr,
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CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
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/* Enable the clock and set the pxclk */
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setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
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iounmap(guts);
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}
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/**
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* p1022ds_valid_monitor_port: set the monitor port for sysfs
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*/
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enum fsl_diu_monitor_port
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p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
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{
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switch (port) {
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case FSL_DIU_PORT_DVI:
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case FSL_DIU_PORT_LVDS:
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return port;
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default:
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return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
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}
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}
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#endif
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void __init p1022_ds_pic_init(void)
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{
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struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
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MPIC_SINGLE_DEST_CPU,
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0, 256, " OpenPIC ");
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BUG_ON(mpic == NULL);
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mpic_init(mpic);
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}
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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/*
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* Disables a node in the device tree.
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*
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* This function is called before kmalloc() is available, so the 'new' object
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* should be allocated in the global area. The easiest way is to do that is
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* to allocate one static local variable for each call to this function.
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*/
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static void __init disable_one_node(struct device_node *np, struct property *new)
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{
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struct property *old;
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old = of_find_property(np, new->name, NULL);
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if (old)
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prom_update_property(np, new, old);
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else
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prom_add_property(np, new);
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}
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/* TRUE if there is a "video=fslfb" command-line parameter. */
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static bool fslfb;
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/*
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* Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
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* true if we find it.
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*
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* We need to use early_param() instead of __setup() because the normal
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* __setup() gets called to late. However, early_param() gets called very
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* early, before the device tree is unflattened, so all we can do now is set a
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* global variable. Later on, p1022_ds_setup_arch() will use that variable
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* to determine if we need to update the device tree.
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*/
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static int __init early_video_setup(char *options)
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{
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fslfb = (strncmp(options, "fslfb:", 6) == 0);
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return 0;
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}
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early_param("video", early_video_setup);
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#endif
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/*
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* Setup the architecture
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*/
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static void __init p1022_ds_setup_arch(void)
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{
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#ifdef CONFIG_PCI
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struct device_node *np;
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#endif
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dma_addr_t max = 0xffffffff;
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if (ppc_md.progress)
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ppc_md.progress("p1022_ds_setup_arch()", 0);
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#ifdef CONFIG_PCI
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for_each_compatible_node(np, "pci", "fsl,p1022-pcie") {
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struct resource rsrc;
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struct pci_controller *hose;
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of_address_to_resource(np, 0, &rsrc);
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if ((rsrc.start & 0xfffff) == 0x8000)
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fsl_add_bridge(np, 1);
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else
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fsl_add_bridge(np, 0);
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hose = pci_find_hose_for_OF_device(np);
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max = min(max, hose->dma_window_base_cur +
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hose->dma_window_size);
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}
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#endif
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#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
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diu_ops.get_pixel_format = p1022ds_get_pixel_format;
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diu_ops.set_gamma_table = p1022ds_set_gamma_table;
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diu_ops.set_monitor_port = p1022ds_set_monitor_port;
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diu_ops.set_pixel_clock = p1022ds_set_pixel_clock;
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diu_ops.valid_monitor_port = p1022ds_valid_monitor_port;
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/*
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* Disable the NOR flash node if there is video=fslfb... command-line
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* parameter. When the DIU is active, NOR flash is unavailable, so we
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* have to disable the node before the MTD driver loads.
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*/
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if (fslfb) {
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struct device_node *np =
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of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
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if (np) {
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np = of_find_compatible_node(np, NULL, "cfi-flash");
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if (np) {
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static struct property nor_status = {
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.name = "status",
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.value = "disabled",
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.length = sizeof("disabled"),
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};
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pr_info("p1022ds: disabling %s node",
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np->full_name);
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disable_one_node(np, &nor_status);
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of_node_put(np);
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}
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}
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}
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#endif
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mpc85xx_smp_init();
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#ifdef CONFIG_SWIOTLB
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if (memblock_end_of_DRAM() > max) {
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ppc_swiotlb_enable = 1;
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set_pci_dma_ops(&swiotlb_dma_ops);
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ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_swiotlb;
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}
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#endif
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pr_info("Freescale P1022 DS reference board\n");
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}
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|
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machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
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|
|
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machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
|
|
|
|
/*
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|
* Called very early, device-tree isn't unflattened
|
|
*/
|
|
static int __init p1022_ds_probe(void)
|
|
{
|
|
unsigned long root = of_get_flat_dt_root();
|
|
|
|
return of_flat_dt_is_compatible(root, "fsl,p1022ds");
|
|
}
|
|
|
|
define_machine(p1022_ds) {
|
|
.name = "P1022 DS",
|
|
.probe = p1022_ds_probe,
|
|
.setup_arch = p1022_ds_setup_arch,
|
|
.init_IRQ = p1022_ds_pic_init,
|
|
#ifdef CONFIG_PCI
|
|
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
|
#endif
|
|
.get_irq = mpic_get_irq,
|
|
.restart = fsl_rstcr_restart,
|
|
.calibrate_decr = generic_calibrate_decr,
|
|
.progress = udbg_progress,
|
|
};
|