7fd0db5b6e
There is no need to include <linux/pinctrl/consumer.h> as no pinctrl function is used in this driver, so just remove it. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
760 lines
20 KiB
C
760 lines
20 KiB
C
/*
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* Driver for Atmel QSPI Controller
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*
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* Copyright (C) 2015 Atmel Corporation
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*
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* Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/spi-nor.h>
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#include <linux/platform_data/atmel.h>
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#include <linux/of.h>
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#include <linux/io.h>
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#include <linux/gpio.h>
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/* QSPI register offsets */
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#define QSPI_CR 0x0000 /* Control Register */
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#define QSPI_MR 0x0004 /* Mode Register */
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#define QSPI_RD 0x0008 /* Receive Data Register */
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#define QSPI_TD 0x000c /* Transmit Data Register */
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#define QSPI_SR 0x0010 /* Status Register */
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#define QSPI_IER 0x0014 /* Interrupt Enable Register */
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#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
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#define QSPI_IMR 0x001c /* Interrupt Mask Register */
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#define QSPI_SCR 0x0020 /* Serial Clock Register */
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#define QSPI_IAR 0x0030 /* Instruction Address Register */
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#define QSPI_ICR 0x0034 /* Instruction Code Register */
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#define QSPI_IFR 0x0038 /* Instruction Frame Register */
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#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
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#define QSPI_SKR 0x0044 /* Scrambling Key Register */
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#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
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#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
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#define QSPI_VERSION 0x00FC /* Version Register */
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/* Bitfields in QSPI_CR (Control Register) */
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#define QSPI_CR_QSPIEN BIT(0)
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#define QSPI_CR_QSPIDIS BIT(1)
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#define QSPI_CR_SWRST BIT(7)
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#define QSPI_CR_LASTXFER BIT(24)
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/* Bitfields in QSPI_MR (Mode Register) */
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#define QSPI_MR_SSM BIT(0)
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#define QSPI_MR_LLB BIT(1)
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#define QSPI_MR_WDRBT BIT(2)
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#define QSPI_MR_SMRM BIT(3)
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#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
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#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
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#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
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#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
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#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
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#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
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#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
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#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
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#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
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#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
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/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
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#define QSPI_SR_RDRF BIT(0)
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#define QSPI_SR_TDRE BIT(1)
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#define QSPI_SR_TXEMPTY BIT(2)
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#define QSPI_SR_OVRES BIT(3)
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#define QSPI_SR_CSR BIT(8)
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#define QSPI_SR_CSS BIT(9)
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#define QSPI_SR_INSTRE BIT(10)
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#define QSPI_SR_QSPIENS BIT(24)
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#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
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/* Bitfields in QSPI_SCR (Serial Clock Register) */
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#define QSPI_SCR_CPOL BIT(0)
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#define QSPI_SCR_CPHA BIT(1)
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#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
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#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
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#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
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#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
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/* Bitfields in QSPI_ICR (Instruction Code Register) */
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#define QSPI_ICR_INST_MASK GENMASK(7, 0)
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#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
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#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
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#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
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/* Bitfields in QSPI_IFR (Instruction Frame Register) */
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#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
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#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
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#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
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#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
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#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
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#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
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#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
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#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
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#define QSPI_IFR_INSTEN BIT(4)
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#define QSPI_IFR_ADDREN BIT(5)
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#define QSPI_IFR_OPTEN BIT(6)
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#define QSPI_IFR_DATAEN BIT(7)
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#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
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#define QSPI_IFR_OPTL_1BIT (0 << 8)
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#define QSPI_IFR_OPTL_2BIT (1 << 8)
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#define QSPI_IFR_OPTL_4BIT (2 << 8)
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#define QSPI_IFR_OPTL_8BIT (3 << 8)
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#define QSPI_IFR_ADDRL BIT(10)
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#define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12)
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#define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12)
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#define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12)
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#define QSPI_IFR_TFRTYP_TRSFR_WRITE (2 << 12)
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#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM (3 << 13)
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#define QSPI_IFR_CRM BIT(14)
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#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
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#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
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/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
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#define QSPI_SMR_SCREN BIT(0)
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#define QSPI_SMR_RVDIS BIT(1)
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/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
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#define QSPI_WPMR_WPEN BIT(0)
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#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
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#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
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/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
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#define QSPI_WPSR_WPVS BIT(0)
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#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
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#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
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struct atmel_qspi {
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void __iomem *regs;
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void __iomem *mem;
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struct clk *clk;
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struct platform_device *pdev;
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u32 pending;
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struct spi_nor nor;
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u32 clk_rate;
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struct completion cmd_completion;
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};
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struct atmel_qspi_command {
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union {
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struct {
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u32 instruction:1;
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u32 address:3;
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u32 mode:1;
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u32 dummy:1;
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u32 data:1;
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u32 reserved:25;
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} bits;
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u32 word;
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} enable;
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u8 instruction;
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u8 mode;
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u8 num_mode_cycles;
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u8 num_dummy_cycles;
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u32 address;
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size_t buf_len;
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const void *tx_buf;
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void *rx_buf;
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};
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/* Register access functions */
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static inline u32 qspi_readl(struct atmel_qspi *aq, u32 reg)
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{
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return readl_relaxed(aq->regs + reg);
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}
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static inline void qspi_writel(struct atmel_qspi *aq, u32 reg, u32 value)
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{
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writel_relaxed(value, aq->regs + reg);
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}
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static int atmel_qspi_run_transfer(struct atmel_qspi *aq,
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const struct atmel_qspi_command *cmd)
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{
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void __iomem *ahb_mem;
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/* Then fallback to a PIO transfer (memcpy() DOES NOT work!) */
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ahb_mem = aq->mem;
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if (cmd->enable.bits.address)
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ahb_mem += cmd->address;
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if (cmd->tx_buf)
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_memcpy_toio(ahb_mem, cmd->tx_buf, cmd->buf_len);
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else
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_memcpy_fromio(cmd->rx_buf, ahb_mem, cmd->buf_len);
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return 0;
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}
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#ifdef DEBUG
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static void atmel_qspi_debug_command(struct atmel_qspi *aq,
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const struct atmel_qspi_command *cmd,
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u32 ifr)
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{
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u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
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size_t len = 0;
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int i;
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if (cmd->enable.bits.instruction)
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cmd_buf[len++] = cmd->instruction;
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for (i = cmd->enable.bits.address-1; i >= 0; --i)
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cmd_buf[len++] = (cmd->address >> (i << 3)) & 0xff;
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if (cmd->enable.bits.mode)
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cmd_buf[len++] = cmd->mode;
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if (cmd->enable.bits.dummy) {
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int num = cmd->num_dummy_cycles;
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switch (ifr & QSPI_IFR_WIDTH_MASK) {
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case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
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case QSPI_IFR_WIDTH_DUAL_OUTPUT:
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case QSPI_IFR_WIDTH_QUAD_OUTPUT:
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num >>= 3;
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break;
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case QSPI_IFR_WIDTH_DUAL_IO:
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case QSPI_IFR_WIDTH_DUAL_CMD:
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num >>= 2;
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break;
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case QSPI_IFR_WIDTH_QUAD_IO:
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case QSPI_IFR_WIDTH_QUAD_CMD:
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num >>= 1;
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break;
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default:
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return;
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}
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for (i = 0; i < num; ++i)
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cmd_buf[len++] = 0;
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}
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/* Dump the SPI command */
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print_hex_dump(KERN_DEBUG, "qspi cmd: ", DUMP_PREFIX_NONE,
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32, 1, cmd_buf, len, false);
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#ifdef VERBOSE_DEBUG
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/* If verbose debug is enabled, also dump the TX data */
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if (cmd->enable.bits.data && cmd->tx_buf)
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print_hex_dump(KERN_DEBUG, "qspi tx : ", DUMP_PREFIX_NONE,
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32, 1, cmd->tx_buf, cmd->buf_len, false);
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#endif
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}
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#else
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#define atmel_qspi_debug_command(aq, cmd, ifr)
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#endif
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static int atmel_qspi_run_command(struct atmel_qspi *aq,
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const struct atmel_qspi_command *cmd,
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u32 ifr_tfrtyp, enum spi_nor_protocol proto)
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{
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u32 iar, icr, ifr, sr;
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int err = 0;
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iar = 0;
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icr = 0;
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ifr = ifr_tfrtyp;
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/* Set the SPI protocol */
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switch (proto) {
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case SNOR_PROTO_1_1_1:
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ifr |= QSPI_IFR_WIDTH_SINGLE_BIT_SPI;
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break;
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case SNOR_PROTO_1_1_2:
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ifr |= QSPI_IFR_WIDTH_DUAL_OUTPUT;
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break;
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case SNOR_PROTO_1_1_4:
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ifr |= QSPI_IFR_WIDTH_QUAD_OUTPUT;
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break;
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case SNOR_PROTO_1_2_2:
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ifr |= QSPI_IFR_WIDTH_DUAL_IO;
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break;
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case SNOR_PROTO_1_4_4:
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ifr |= QSPI_IFR_WIDTH_QUAD_IO;
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break;
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case SNOR_PROTO_2_2_2:
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ifr |= QSPI_IFR_WIDTH_DUAL_CMD;
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break;
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case SNOR_PROTO_4_4_4:
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ifr |= QSPI_IFR_WIDTH_QUAD_CMD;
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break;
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default:
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return -EINVAL;
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}
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/* Compute instruction parameters */
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if (cmd->enable.bits.instruction) {
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icr |= QSPI_ICR_INST(cmd->instruction);
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ifr |= QSPI_IFR_INSTEN;
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}
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/* Compute address parameters */
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switch (cmd->enable.bits.address) {
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case 4:
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ifr |= QSPI_IFR_ADDRL;
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/* fall through to the 24bit (3 byte) address case. */
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case 3:
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iar = (cmd->enable.bits.data) ? 0 : cmd->address;
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ifr |= QSPI_IFR_ADDREN;
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break;
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case 0:
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break;
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default:
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return -EINVAL;
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}
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/* Compute option parameters */
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if (cmd->enable.bits.mode && cmd->num_mode_cycles) {
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u32 mode_cycle_bits, mode_bits;
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icr |= QSPI_ICR_OPT(cmd->mode);
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ifr |= QSPI_IFR_OPTEN;
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switch (ifr & QSPI_IFR_WIDTH_MASK) {
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case QSPI_IFR_WIDTH_SINGLE_BIT_SPI:
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case QSPI_IFR_WIDTH_DUAL_OUTPUT:
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case QSPI_IFR_WIDTH_QUAD_OUTPUT:
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mode_cycle_bits = 1;
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break;
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case QSPI_IFR_WIDTH_DUAL_IO:
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case QSPI_IFR_WIDTH_DUAL_CMD:
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mode_cycle_bits = 2;
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break;
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case QSPI_IFR_WIDTH_QUAD_IO:
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case QSPI_IFR_WIDTH_QUAD_CMD:
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mode_cycle_bits = 4;
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break;
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default:
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return -EINVAL;
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}
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mode_bits = cmd->num_mode_cycles * mode_cycle_bits;
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switch (mode_bits) {
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case 1:
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ifr |= QSPI_IFR_OPTL_1BIT;
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break;
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case 2:
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ifr |= QSPI_IFR_OPTL_2BIT;
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break;
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case 4:
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ifr |= QSPI_IFR_OPTL_4BIT;
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break;
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case 8:
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ifr |= QSPI_IFR_OPTL_8BIT;
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break;
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default:
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return -EINVAL;
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}
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}
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/* Set number of dummy cycles */
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if (cmd->enable.bits.dummy)
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ifr |= QSPI_IFR_NBDUM(cmd->num_dummy_cycles);
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/* Set data enable */
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if (cmd->enable.bits.data) {
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ifr |= QSPI_IFR_DATAEN;
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/* Special case for Continuous Read Mode */
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if (!cmd->tx_buf && !cmd->rx_buf)
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ifr |= QSPI_IFR_CRM;
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}
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/* Clear pending interrupts */
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(void)qspi_readl(aq, QSPI_SR);
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/* Set QSPI Instruction Frame registers */
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atmel_qspi_debug_command(aq, cmd, ifr);
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qspi_writel(aq, QSPI_IAR, iar);
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qspi_writel(aq, QSPI_ICR, icr);
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qspi_writel(aq, QSPI_IFR, ifr);
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/* Skip to the final steps if there is no data */
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if (!cmd->enable.bits.data)
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goto no_data;
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/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
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(void)qspi_readl(aq, QSPI_IFR);
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/* Stop here for continuous read */
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if (!cmd->tx_buf && !cmd->rx_buf)
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return 0;
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/* Send/Receive data */
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err = atmel_qspi_run_transfer(aq, cmd);
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/* Release the chip-select */
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qspi_writel(aq, QSPI_CR, QSPI_CR_LASTXFER);
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if (err)
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return err;
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#if defined(DEBUG) && defined(VERBOSE_DEBUG)
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/*
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* If verbose debug is enabled, also dump the RX data in addition to
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* the SPI command previously dumped by atmel_qspi_debug_command()
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*/
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if (cmd->rx_buf)
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print_hex_dump(KERN_DEBUG, "qspi rx : ", DUMP_PREFIX_NONE,
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32, 1, cmd->rx_buf, cmd->buf_len, false);
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#endif
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no_data:
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/* Poll INSTRuction End status */
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sr = qspi_readl(aq, QSPI_SR);
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if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
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return err;
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/* Wait for INSTRuction End interrupt */
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reinit_completion(&aq->cmd_completion);
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aq->pending = sr & QSPI_SR_CMD_COMPLETED;
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qspi_writel(aq, QSPI_IER, QSPI_SR_CMD_COMPLETED);
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if (!wait_for_completion_timeout(&aq->cmd_completion,
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msecs_to_jiffies(1000)))
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err = -ETIMEDOUT;
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qspi_writel(aq, QSPI_IDR, QSPI_SR_CMD_COMPLETED);
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return err;
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}
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static int atmel_qspi_read_reg(struct spi_nor *nor, u8 opcode,
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u8 *buf, int len)
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{
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struct atmel_qspi *aq = nor->priv;
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struct atmel_qspi_command cmd;
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memset(&cmd, 0, sizeof(cmd));
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cmd.enable.bits.instruction = 1;
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cmd.enable.bits.data = 1;
|
|
cmd.instruction = opcode;
|
|
cmd.rx_buf = buf;
|
|
cmd.buf_len = len;
|
|
return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ,
|
|
nor->reg_proto);
|
|
}
|
|
|
|
static int atmel_qspi_write_reg(struct spi_nor *nor, u8 opcode,
|
|
u8 *buf, int len)
|
|
{
|
|
struct atmel_qspi *aq = nor->priv;
|
|
struct atmel_qspi_command cmd;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.enable.bits.instruction = 1;
|
|
cmd.enable.bits.data = (buf != NULL && len > 0);
|
|
cmd.instruction = opcode;
|
|
cmd.tx_buf = buf;
|
|
cmd.buf_len = len;
|
|
return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
|
|
nor->reg_proto);
|
|
}
|
|
|
|
static ssize_t atmel_qspi_write(struct spi_nor *nor, loff_t to, size_t len,
|
|
const u_char *write_buf)
|
|
{
|
|
struct atmel_qspi *aq = nor->priv;
|
|
struct atmel_qspi_command cmd;
|
|
ssize_t ret;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.enable.bits.instruction = 1;
|
|
cmd.enable.bits.address = nor->addr_width;
|
|
cmd.enable.bits.data = 1;
|
|
cmd.instruction = nor->program_opcode;
|
|
cmd.address = (u32)to;
|
|
cmd.tx_buf = write_buf;
|
|
cmd.buf_len = len;
|
|
ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE_MEM,
|
|
nor->write_proto);
|
|
return (ret < 0) ? ret : len;
|
|
}
|
|
|
|
static int atmel_qspi_erase(struct spi_nor *nor, loff_t offs)
|
|
{
|
|
struct atmel_qspi *aq = nor->priv;
|
|
struct atmel_qspi_command cmd;
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.enable.bits.instruction = 1;
|
|
cmd.enable.bits.address = nor->addr_width;
|
|
cmd.instruction = nor->erase_opcode;
|
|
cmd.address = (u32)offs;
|
|
return atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_WRITE,
|
|
nor->reg_proto);
|
|
}
|
|
|
|
static ssize_t atmel_qspi_read(struct spi_nor *nor, loff_t from, size_t len,
|
|
u_char *read_buf)
|
|
{
|
|
struct atmel_qspi *aq = nor->priv;
|
|
struct atmel_qspi_command cmd;
|
|
u8 num_mode_cycles, num_dummy_cycles;
|
|
ssize_t ret;
|
|
|
|
if (nor->read_dummy >= 2) {
|
|
num_mode_cycles = 2;
|
|
num_dummy_cycles = nor->read_dummy - 2;
|
|
} else {
|
|
num_mode_cycles = nor->read_dummy;
|
|
num_dummy_cycles = 0;
|
|
}
|
|
|
|
memset(&cmd, 0, sizeof(cmd));
|
|
cmd.enable.bits.instruction = 1;
|
|
cmd.enable.bits.address = nor->addr_width;
|
|
cmd.enable.bits.mode = (num_mode_cycles > 0);
|
|
cmd.enable.bits.dummy = (num_dummy_cycles > 0);
|
|
cmd.enable.bits.data = 1;
|
|
cmd.instruction = nor->read_opcode;
|
|
cmd.address = (u32)from;
|
|
cmd.mode = 0xff; /* This value prevents from entering the 0-4-4 mode */
|
|
cmd.num_mode_cycles = num_mode_cycles;
|
|
cmd.num_dummy_cycles = num_dummy_cycles;
|
|
cmd.rx_buf = read_buf;
|
|
cmd.buf_len = len;
|
|
ret = atmel_qspi_run_command(aq, &cmd, QSPI_IFR_TFRTYP_TRSFR_READ_MEM,
|
|
nor->read_proto);
|
|
return (ret < 0) ? ret : len;
|
|
}
|
|
|
|
static int atmel_qspi_init(struct atmel_qspi *aq)
|
|
{
|
|
unsigned long src_rate;
|
|
u32 mr, scr, scbr;
|
|
|
|
/* Reset the QSPI controller */
|
|
qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
|
|
|
|
/* Set the QSPI controller in Serial Memory Mode */
|
|
mr = QSPI_MR_NBBITS(8) | QSPI_MR_SSM;
|
|
qspi_writel(aq, QSPI_MR, mr);
|
|
|
|
src_rate = clk_get_rate(aq->clk);
|
|
if (!src_rate)
|
|
return -EINVAL;
|
|
|
|
/* Compute the QSPI baudrate */
|
|
scbr = DIV_ROUND_UP(src_rate, aq->clk_rate);
|
|
if (scbr > 0)
|
|
scbr--;
|
|
scr = QSPI_SCR_SCBR(scbr);
|
|
qspi_writel(aq, QSPI_SCR, scr);
|
|
|
|
/* Enable the QSPI controller */
|
|
qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
|
|
{
|
|
struct atmel_qspi *aq = (struct atmel_qspi *)dev_id;
|
|
u32 status, mask, pending;
|
|
|
|
status = qspi_readl(aq, QSPI_SR);
|
|
mask = qspi_readl(aq, QSPI_IMR);
|
|
pending = status & mask;
|
|
|
|
if (!pending)
|
|
return IRQ_NONE;
|
|
|
|
aq->pending |= pending;
|
|
if ((aq->pending & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
|
|
complete(&aq->cmd_completion);
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static int atmel_qspi_probe(struct platform_device *pdev)
|
|
{
|
|
const struct spi_nor_hwcaps hwcaps = {
|
|
.mask = SNOR_HWCAPS_READ |
|
|
SNOR_HWCAPS_READ_FAST |
|
|
SNOR_HWCAPS_READ_1_1_2 |
|
|
SNOR_HWCAPS_READ_1_2_2 |
|
|
SNOR_HWCAPS_READ_2_2_2 |
|
|
SNOR_HWCAPS_READ_1_1_4 |
|
|
SNOR_HWCAPS_READ_1_4_4 |
|
|
SNOR_HWCAPS_READ_4_4_4 |
|
|
SNOR_HWCAPS_PP |
|
|
SNOR_HWCAPS_PP_1_1_4 |
|
|
SNOR_HWCAPS_PP_1_4_4 |
|
|
SNOR_HWCAPS_PP_4_4_4,
|
|
};
|
|
struct device_node *child, *np = pdev->dev.of_node;
|
|
struct atmel_qspi *aq;
|
|
struct resource *res;
|
|
struct spi_nor *nor;
|
|
struct mtd_info *mtd;
|
|
int irq, err = 0;
|
|
|
|
if (of_get_child_count(np) != 1)
|
|
return -ENODEV;
|
|
child = of_get_next_child(np, NULL);
|
|
|
|
aq = devm_kzalloc(&pdev->dev, sizeof(*aq), GFP_KERNEL);
|
|
if (!aq) {
|
|
err = -ENOMEM;
|
|
goto exit;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, aq);
|
|
init_completion(&aq->cmd_completion);
|
|
aq->pdev = pdev;
|
|
|
|
/* Map the registers */
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base");
|
|
aq->regs = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(aq->regs)) {
|
|
dev_err(&pdev->dev, "missing registers\n");
|
|
err = PTR_ERR(aq->regs);
|
|
goto exit;
|
|
}
|
|
|
|
/* Map the AHB memory */
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_mmap");
|
|
aq->mem = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(aq->mem)) {
|
|
dev_err(&pdev->dev, "missing AHB memory\n");
|
|
err = PTR_ERR(aq->mem);
|
|
goto exit;
|
|
}
|
|
|
|
/* Get the peripheral clock */
|
|
aq->clk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(aq->clk)) {
|
|
dev_err(&pdev->dev, "missing peripheral clock\n");
|
|
err = PTR_ERR(aq->clk);
|
|
goto exit;
|
|
}
|
|
|
|
/* Enable the peripheral clock */
|
|
err = clk_prepare_enable(aq->clk);
|
|
if (err) {
|
|
dev_err(&pdev->dev, "failed to enable the peripheral clock\n");
|
|
goto exit;
|
|
}
|
|
|
|
/* Request the IRQ */
|
|
irq = platform_get_irq(pdev, 0);
|
|
if (irq < 0) {
|
|
dev_err(&pdev->dev, "missing IRQ\n");
|
|
err = irq;
|
|
goto disable_clk;
|
|
}
|
|
err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt,
|
|
0, dev_name(&pdev->dev), aq);
|
|
if (err)
|
|
goto disable_clk;
|
|
|
|
/* Setup the spi-nor */
|
|
nor = &aq->nor;
|
|
mtd = &nor->mtd;
|
|
|
|
nor->dev = &pdev->dev;
|
|
spi_nor_set_flash_node(nor, child);
|
|
nor->priv = aq;
|
|
mtd->priv = nor;
|
|
|
|
nor->read_reg = atmel_qspi_read_reg;
|
|
nor->write_reg = atmel_qspi_write_reg;
|
|
nor->read = atmel_qspi_read;
|
|
nor->write = atmel_qspi_write;
|
|
nor->erase = atmel_qspi_erase;
|
|
|
|
err = of_property_read_u32(child, "spi-max-frequency", &aq->clk_rate);
|
|
if (err < 0)
|
|
goto disable_clk;
|
|
|
|
err = atmel_qspi_init(aq);
|
|
if (err)
|
|
goto disable_clk;
|
|
|
|
err = spi_nor_scan(nor, NULL, &hwcaps);
|
|
if (err)
|
|
goto disable_clk;
|
|
|
|
err = mtd_device_register(mtd, NULL, 0);
|
|
if (err)
|
|
goto disable_clk;
|
|
|
|
of_node_put(child);
|
|
|
|
return 0;
|
|
|
|
disable_clk:
|
|
clk_disable_unprepare(aq->clk);
|
|
exit:
|
|
of_node_put(child);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int atmel_qspi_remove(struct platform_device *pdev)
|
|
{
|
|
struct atmel_qspi *aq = platform_get_drvdata(pdev);
|
|
|
|
mtd_device_unregister(&aq->nor.mtd);
|
|
qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIDIS);
|
|
clk_disable_unprepare(aq->clk);
|
|
return 0;
|
|
}
|
|
|
|
|
|
static const struct of_device_id atmel_qspi_dt_ids[] = {
|
|
{ .compatible = "atmel,sama5d2-qspi" },
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, atmel_qspi_dt_ids);
|
|
|
|
static struct platform_driver atmel_qspi_driver = {
|
|
.driver = {
|
|
.name = "atmel_qspi",
|
|
.of_match_table = atmel_qspi_dt_ids,
|
|
},
|
|
.probe = atmel_qspi_probe,
|
|
.remove = atmel_qspi_remove,
|
|
};
|
|
module_platform_driver(atmel_qspi_driver);
|
|
|
|
MODULE_AUTHOR("Cyrille Pitchen <cyrille.pitchen@atmel.com>");
|
|
MODULE_DESCRIPTION("Atmel QSPI Controller driver");
|
|
MODULE_LICENSE("GPL v2");
|