21f47fbc5b
This adds support for the family of Systems-on-Chip produced initially by VIA and now its subsidiary WonderMedia that have recently become widespread in lower-end Chinese ARM-based tablets and netbooks. Support is included for both VT8500 and WM8505, selectable by a configuration switch at kernel build time. Included are basic machine initialization files, register and interrupt definitions, support for the on-chip interrupt controller, high-precision OS timer, GPIO lines, necessary macros for early debug, pulse-width-modulated outputs control, as well as platform device configurations for the specific drivers implemented elsewhere. Signed-off-by: Alexey Charkov <alchark@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
155 lines
4.5 KiB
C
155 lines
4.5 KiB
C
/*
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* arch/arm/mach-vt8500/timer.c
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*
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* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/delay.h>
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#include <asm/mach/time.h>
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#include "devices.h"
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#define VT8500_TIMER_OFFSET 0x0100
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#define TIMER_MATCH_VAL 0x0000
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#define TIMER_COUNT_VAL 0x0010
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#define TIMER_STATUS_VAL 0x0014
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#define TIMER_IER_VAL 0x001c /* interrupt enable */
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#define TIMER_CTRL_VAL 0x0020
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#define TIMER_AS_VAL 0x0024 /* access status */
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#define TIMER_COUNT_R_ACTIVE (1 << 5) /* not ready for read */
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#define TIMER_COUNT_W_ACTIVE (1 << 4) /* not ready for write */
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#define TIMER_MATCH_W_ACTIVE (1 << 0) /* not ready for write */
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#define VT8500_TIMER_HZ 3000000
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#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
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static void __iomem *regbase;
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static cycle_t vt8500_timer_read(struct clocksource *cs)
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{
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int loops = msecs_to_loops(10);
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writel(3, regbase + TIMER_CTRL_VAL);
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while ((readl((regbase + TIMER_AS_VAL)) & TIMER_COUNT_R_ACTIVE)
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&& --loops)
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cpu_relax();
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return readl(regbase + TIMER_COUNT_VAL);
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}
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struct clocksource clocksource = {
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.name = "vt8500_timer",
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.rating = 200,
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.read = vt8500_timer_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int vt8500_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *evt)
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{
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int loops = msecs_to_loops(10);
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cycle_t alarm = clocksource.read(&clocksource) + cycles;
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while ((readl(regbase + TIMER_AS_VAL) & TIMER_MATCH_W_ACTIVE)
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&& --loops)
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cpu_relax();
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writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL);
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if ((signed)(alarm - clocksource.read(&clocksource)) <= 16)
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return -ETIME;
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writel(1, regbase + TIMER_IER_VAL);
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return 0;
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}
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static void vt8500_timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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switch (mode) {
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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writel(readl(regbase + TIMER_CTRL_VAL) | 1,
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regbase + TIMER_CTRL_VAL);
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writel(0, regbase + TIMER_IER_VAL);
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break;
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}
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}
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struct clock_event_device clockevent = {
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.name = "vt8500_timer",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.rating = 200,
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.set_next_event = vt8500_timer_set_next_event,
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.set_mode = vt8500_timer_set_mode,
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};
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static irqreturn_t vt8500_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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writel(0xf, regbase + TIMER_STATUS_VAL);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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struct irqaction irq = {
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.name = "vt8500_timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = vt8500_timer_interrupt,
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.dev_id = &clockevent,
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};
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static void __init vt8500_timer_init(void)
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{
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regbase = ioremap(wmt_pmc_base + VT8500_TIMER_OFFSET, 0x28);
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if (!regbase)
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printk(KERN_ERR "vt8500_timer_init: failed to map MMIO registers\n");
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writel(1, regbase + TIMER_CTRL_VAL);
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writel(0xf, regbase + TIMER_STATUS_VAL);
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writel(~0, regbase + TIMER_MATCH_VAL);
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if (clocksource_register_hz(&clocksource, VT8500_TIMER_HZ))
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printk(KERN_ERR "vt8500_timer_init: clocksource_register failed for %s\n",
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clocksource.name);
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clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
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/* copy-pasted from mach-msm; no idea */
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clockevent.max_delta_ns =
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clockevent_delta2ns(0xf0000000, &clockevent);
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clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
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clockevent.cpumask = cpumask_of(0);
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if (setup_irq(wmt_timer_irq, &irq))
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printk(KERN_ERR "vt8500_timer_init: setup_irq failed for %s\n",
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clockevent.name);
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clockevents_register_device(&clockevent);
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}
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struct sys_timer vt8500_timer = {
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.init = vt8500_timer_init
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};
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