9a8fd55899
The attached patches provides part 6 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
37 lines
815 B
C
37 lines
815 B
C
/*
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* include/asm-xtensa/irq.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 - 2005 Tensilica Inc.
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*/
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#ifndef _XTENSA_IRQ_H
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#define _XTENSA_IRQ_H
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#include <linux/config.h>
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#include <asm/platform/hardware.h>
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#include <xtensa/config/core.h>
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#ifndef PLATFORM_NR_IRQS
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# define PLATFORM_NR_IRQS 0
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#endif
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#define XTENSA_NR_IRQS XCHAL_NUM_INTERRUPTS
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#define NR_IRQS (XTENSA_NR_IRQS + PLATFORM_NR_IRQS)
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static __inline__ int irq_canonicalize(int irq)
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{
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return (irq);
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}
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struct irqaction;
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#if 0 // FIXME
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extern void disable_irq_nosync(unsigned int);
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extern void disable_irq(unsigned int);
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extern void enable_irq(unsigned int);
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#endif
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#endif /* _XTENSA_IRQ_H */
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