1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
274 lines
7.3 KiB
C
274 lines
7.3 KiB
C
/*
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* arch/ppc/boot/spruce/misc.c
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*
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* Misc. bootloader code for IBM Spruce reference platform
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*
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* Authors: Johnnie Peters <jpeters@mvista.com>
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* Matt Porter <mporter@mvista.com>
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*
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* Derived from arch/ppc/boot/prep/misc.c
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*
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* 2000-2001 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/types.h>
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#include <linux/config.h>
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#include <linux/pci.h>
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#include <asm/bootinfo.h>
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extern unsigned long decompress_kernel(unsigned long load_addr, int num_words,
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unsigned long cksum);
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/* Define some important locations of the Spruce. */
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#define SPRUCE_PCI_CONFIG_ADDR 0xfec00000
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#define SPRUCE_PCI_CONFIG_DATA 0xfec00004
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/* PCI configuration space access routines. */
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unsigned int *pci_config_address = (unsigned int *)SPRUCE_PCI_CONFIG_ADDR;
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unsigned char *pci_config_data = (unsigned char *)SPRUCE_PCI_CONFIG_DATA;
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void cpc700_pcibios_read_config_byte(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned char *val)
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{
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out_le32(pci_config_address,
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(((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
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*val= (in_le32((unsigned *)pci_config_data) >> (8 * (offset & 3))) & 0xff;
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}
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void cpc700_pcibios_write_config_byte(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned char val)
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{
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out_le32(pci_config_address,
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(((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
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out_8(pci_config_data + (offset&3), val);
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}
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void cpc700_pcibios_read_config_word(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned short *val)
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{
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out_le32(pci_config_address,
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(((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
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*val= in_le16((unsigned short *)(pci_config_data + (offset&3)));
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}
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void cpc700_pcibios_write_config_word(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned short val)
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{
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out_le32(pci_config_address,
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(((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
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out_le16((unsigned short *)(pci_config_data + (offset&3)), val);
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}
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void cpc700_pcibios_read_config_dword(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned int *val)
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{
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out_le32(pci_config_address,
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(((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
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*val= in_le32((unsigned *)pci_config_data);
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}
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void cpc700_pcibios_write_config_dword(unsigned char bus, unsigned char dev_fn,
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unsigned char offset, unsigned int val)
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{
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out_le32(pci_config_address,
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(((bus & 0xff)<<16) | (dev_fn<<8) | (offset&0xfc) | 0x80000000));
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out_le32((unsigned *)pci_config_data, val);
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}
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#define PCNET32_WIO_RDP 0x10
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#define PCNET32_WIO_RAP 0x12
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#define PCNET32_WIO_RESET 0x14
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#define PCNET32_DWIO_RDP 0x10
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#define PCNET32_DWIO_RAP 0x14
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#define PCNET32_DWIO_RESET 0x18
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/* Processor interface config register access */
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#define PIFCFGADDR 0xff500000
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#define PIFCFGDATA 0xff500004
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#define PLBMIFOPT 0x18 /* PLB Master Interface Options */
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#define MEM_MBEN 0x24
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#define MEM_TYPE 0x28
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#define MEM_B1SA 0x3c
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#define MEM_B1EA 0x5c
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#define MEM_B2SA 0x40
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#define MEM_B2EA 0x60
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unsigned long
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get_mem_size(void)
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{
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int loop;
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unsigned long mem_size = 0;
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unsigned long mem_mben;
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unsigned long mem_type;
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unsigned long mem_start;
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unsigned long mem_end;
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volatile int *mem_addr = (int *)0xff500008;
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volatile int *mem_data = (int *)0xff50000c;
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/* Get the size of memory from the memory controller. */
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*mem_addr = MEM_MBEN;
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asm("sync");
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mem_mben = *mem_data;
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asm("sync");
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for(loop = 0; loop < 1000; loop++);
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*mem_addr = MEM_TYPE;
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asm("sync");
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mem_type = *mem_data;
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asm("sync");
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for(loop = 0; loop < 1000; loop++);
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*mem_addr = MEM_TYPE;
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/* Confirm bank 1 has DRAM memory */
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if ((mem_mben & 0x40000000) &&
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((mem_type & 0x30000000) == 0x10000000)) {
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*mem_addr = MEM_B1SA;
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asm("sync");
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mem_start = *mem_data;
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asm("sync");
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for(loop = 0; loop < 1000; loop++);
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*mem_addr = MEM_B1EA;
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asm("sync");
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mem_end = *mem_data;
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asm("sync");
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for(loop = 0; loop < 1000; loop++);
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mem_size = mem_end - mem_start + 0x100000;
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}
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/* Confirm bank 2 has DRAM memory */
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if ((mem_mben & 0x20000000) &&
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((mem_type & 0xc000000) == 0x4000000)) {
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*mem_addr = MEM_B2SA;
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asm("sync");
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mem_start = *mem_data;
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asm("sync");
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for(loop = 0; loop < 1000; loop++);
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*mem_addr = MEM_B2EA;
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asm("sync");
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mem_end = *mem_data;
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asm("sync");
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for(loop = 0; loop < 1000; loop++);
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mem_size += mem_end - mem_start + 0x100000;
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}
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return mem_size;
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}
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unsigned long
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load_kernel(unsigned long load_addr, int num_words, unsigned long cksum,
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void *ign1, void *ign2)
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{
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int csr0;
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int csr_id;
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int pci_devfn;
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int found_multi = 0;
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unsigned short vendor;
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unsigned short device;
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unsigned short command;
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unsigned char header_type;
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unsigned int bar0;
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volatile int *pif_addr = (int *)0xff500000;
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volatile int *pif_data = (int *)0xff500004;
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/*
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* Gah, these firmware guys need to learn that hardware
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* byte swapping is evil! Disable all hardware byte
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* swapping so it doesn't hurt anyone.
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*/
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*pif_addr = PLBMIFOPT;
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asm("sync");
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*pif_data = 0x00000000;
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asm("sync");
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/* Search out and turn off the PcNet ethernet boot device. */
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for (pci_devfn = 1; pci_devfn < 0xff; pci_devfn++) {
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if (PCI_FUNC(pci_devfn) && !found_multi)
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continue;
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cpc700_pcibios_read_config_byte(0, pci_devfn,
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PCI_HEADER_TYPE, &header_type);
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if (!PCI_FUNC(pci_devfn))
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found_multi = header_type & 0x80;
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cpc700_pcibios_read_config_word(0, pci_devfn, PCI_VENDOR_ID,
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&vendor);
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if (vendor != 0xffff) {
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cpc700_pcibios_read_config_word(0, pci_devfn,
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PCI_DEVICE_ID, &device);
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/* If this PCI device is the Lance PCNet board then turn it off */
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if ((vendor == PCI_VENDOR_ID_AMD) &&
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(device == PCI_DEVICE_ID_AMD_LANCE)) {
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/* Turn on I/O Space on the board. */
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cpc700_pcibios_read_config_word(0, pci_devfn,
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PCI_COMMAND, &command);
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command |= 0x1;
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cpc700_pcibios_write_config_word(0, pci_devfn,
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PCI_COMMAND, command);
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/* Get the I/O space address */
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cpc700_pcibios_read_config_dword(0, pci_devfn,
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PCI_BASE_ADDRESS_0, &bar0);
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bar0 &= 0xfffffffe;
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/* Reset the PCNet Board */
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inl (bar0+PCNET32_DWIO_RESET);
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inw (bar0+PCNET32_WIO_RESET);
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/* First do a work oriented read of csr0. If the value is
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* 4 then this is the correct mode to access the board.
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* If not try a double word ortiented read.
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*/
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outw(0, bar0 + PCNET32_WIO_RAP);
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csr0 = inw(bar0 + PCNET32_WIO_RDP);
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if (csr0 == 4) {
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/* Check the Chip id register */
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outw(88, bar0 + PCNET32_WIO_RAP);
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csr_id = inw(bar0 + PCNET32_WIO_RDP);
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if (csr_id) {
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/* This is the valid mode - set the stop bit */
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outw(0, bar0 + PCNET32_WIO_RAP);
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outw(csr0, bar0 + PCNET32_WIO_RDP);
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}
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} else {
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outl(0, bar0 + PCNET32_DWIO_RAP);
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csr0 = inl(bar0 + PCNET32_DWIO_RDP);
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if (csr0 == 4) {
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/* Check the Chip id register */
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outl(88, bar0 + PCNET32_WIO_RAP);
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csr_id = inl(bar0 + PCNET32_WIO_RDP);
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if (csr_id) {
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/* This is the valid mode - set the stop bit*/
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outl(0, bar0 + PCNET32_WIO_RAP);
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outl(csr0, bar0 + PCNET32_WIO_RDP);
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}
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}
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}
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}
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}
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}
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return decompress_kernel(load_addr, num_words, cksum);
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}
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