1d1f19cfce
MTTs are allocated in non-cache-coherent memory, so we must give reserved MTTs their own cache line, to prevent both device and CPU from writing into the same cache line at the same time. Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com> |
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| amso1100 | ||
| cxgb3 | ||
| ehca | ||
| ipath | ||
| mthca | ||