db8196df4b
fixup usage of dma direction by introducing dma_transfer_direction, this patch moves dma/drivers/* to use new enum Cc: Jassi Brar <jaswinder.singh@linaro.org> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Viresh Kumar <viresh.kumar@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Mika Westerberg <mika.westerberg@iki.fi> Cc: H Hartley Sweeten <hartleys@visionengravers.com> Cc: Li Yang <leoli@freescale.com> Cc: Zhang Wei <zw@zh-kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Cc: Shawn Guo <shawn.guo@freescale.com> Cc: Yong Wang <yong.y.wang@intel.com> Cc: Tomoya MORINAGA <tomoya-linux@dsn.lapis-semi.com> Cc: Boojin Kim <boojin.kim@samsung.com> Cc: Barry Song <Baohua.Song@csr.com> Acked-by: Mika Westerberg <mika.westerberg@iki.fi> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@st.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
139 lines
4.1 KiB
C
139 lines
4.1 KiB
C
/*
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* Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
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* AVR32 systems.)
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*
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* Copyright (C) 2007 Atmel Corporation
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* Copyright (C) 2010-2011 ST Microelectronics
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DW_DMAC_H
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#define DW_DMAC_H
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#include <linux/dmaengine.h>
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/**
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* struct dw_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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* @is_private: The device channels should be marked as private and not for
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* by the general purpose DMA channel allocator.
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*/
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struct dw_dma_platform_data {
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unsigned int nr_channels;
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bool is_private;
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#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
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#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
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unsigned char chan_allocation_order;
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#define CHAN_PRIORITY_ASCENDING 0 /* chan0 highest */
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#define CHAN_PRIORITY_DESCENDING 1 /* chan7 highest */
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unsigned char chan_priority;
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};
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/**
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* enum dw_dma_slave_width - DMA slave register access width.
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* @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
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* @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
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* @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
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*/
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enum dw_dma_slave_width {
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DW_DMA_SLAVE_WIDTH_8BIT,
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DW_DMA_SLAVE_WIDTH_16BIT,
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DW_DMA_SLAVE_WIDTH_32BIT,
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};
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/* bursts size */
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enum dw_dma_msize {
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DW_DMA_MSIZE_1,
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DW_DMA_MSIZE_4,
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DW_DMA_MSIZE_8,
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DW_DMA_MSIZE_16,
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DW_DMA_MSIZE_32,
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DW_DMA_MSIZE_64,
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DW_DMA_MSIZE_128,
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DW_DMA_MSIZE_256,
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};
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/* flow controller */
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enum dw_dma_fc {
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DW_DMA_FC_D_M2M,
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DW_DMA_FC_D_M2P,
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DW_DMA_FC_D_P2M,
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DW_DMA_FC_D_P2P,
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DW_DMA_FC_P_P2M,
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DW_DMA_FC_SP_P2P,
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DW_DMA_FC_P_M2P,
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DW_DMA_FC_DP_P2P,
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};
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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*
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* @dma_dev: required DMA master device
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* @tx_reg: physical address of data register used for
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* memory-to-peripheral transfers
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* @rx_reg: physical address of data register used for
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* peripheral-to-memory transfers
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* @reg_width: peripheral register width
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* @cfg_hi: Platform-specific initializer for the CFG_HI register
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* @cfg_lo: Platform-specific initializer for the CFG_LO register
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* @src_master: src master for transfers on allocated channel.
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* @dst_master: dest master for transfers on allocated channel.
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* @src_msize: src burst size.
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* @dst_msize: dest burst size.
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* @fc: flow controller for DMA transfer
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*/
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struct dw_dma_slave {
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struct device *dma_dev;
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dma_addr_t tx_reg;
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dma_addr_t rx_reg;
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enum dw_dma_slave_width reg_width;
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u32 cfg_hi;
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u32 cfg_lo;
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u8 src_master;
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u8 dst_master;
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u8 src_msize;
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u8 dst_msize;
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u8 fc;
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};
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/* Platform-configurable bits in CFG_HI */
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#define DWC_CFGH_FCMODE (1 << 0)
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#define DWC_CFGH_FIFO_MODE (1 << 1)
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#define DWC_CFGH_PROTCTL(x) ((x) << 2)
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#define DWC_CFGH_SRC_PER(x) ((x) << 7)
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#define DWC_CFGH_DST_PER(x) ((x) << 11)
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/* Platform-configurable bits in CFG_LO */
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#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
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#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
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#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
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#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
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#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
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#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
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#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
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#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
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#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
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#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
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/* DMA API extensions */
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struct dw_cyclic_desc {
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struct dw_desc **desc;
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unsigned long periods;
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void (*period_callback)(void *param);
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void *period_callback_param;
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};
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struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
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dma_addr_t buf_addr, size_t buf_len, size_t period_len,
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enum dma_transfer_direction direction);
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void dw_dma_cyclic_free(struct dma_chan *chan);
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int dw_dma_cyclic_start(struct dma_chan *chan);
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void dw_dma_cyclic_stop(struct dma_chan *chan);
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dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan);
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dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan);
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#endif /* DW_DMAC_H */
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