Thierry Reding c1d676cec5 clk: tegra: Use the proper parent for plld_dsi ... The current parent, plld_out0, does not exist. The proper name is pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to be more consistent with other clock names. Fixes: b270491eb9 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux") Signed-off-by: Thierry Reding <treding@nvidia.com>		2015-04-10 16:04:22 +02:00
..
clk-audio-sync.c
clk-divider.c	clk: tegra: Implement memory-controller clock	2014-11-26 09:43:23 +01:00
clk-id.h	clk: tegra: Define PLLD_DSI and remove dsia(b)_mux	2015-02-02 16:22:34 +02:00
clk-periph-gate.c	ARM: tegra: Move includes to include/soc/tegra	2014-07-17 13:26:47 +02:00
clk-periph.c	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
clk-pll-out.c
clk-pll.c	clk: tegra: Remove needless initializations	2015-04-10 16:04:18 +02:00
clk-super.c	clk: tegra: Implement locking for super clock	2013-02-12 10:29:12 -07:00
clk-tegra-audio.c	clk: tegra: move audio clk to common file	2013-11-26 18:46:24 +02:00
clk-tegra-fixed.c	clk: tegra: Model oscillator as clock	2015-04-10 16:04:20 +02:00
clk-tegra-periph.c	clk: tegra: Fix a bunch of sparse warnings	2015-04-10 16:03:41 +02:00
clk-tegra-pmc.c	clk: tegra: move PMC, fixed clocks to common files	2013-11-26 18:46:49 +02:00
clk-tegra-super-gen4.c	clk: tegra: cclk_lp has a pllx/2 divider	2014-02-17 16:18:28 +02:00
clk-tegra20.c	clk: tegra: Implement memory-controller clock	2014-11-26 09:43:23 +01:00
clk-tegra30.c	clk: tegra: Model oscillator as clock	2015-04-10 16:04:20 +02:00
clk-tegra114.c	clk: tegra: Use generic tegra_osc_clk_init() on Tegra114	2015-04-10 16:04:21 +02:00
clk-tegra124.c	clk: tegra: Use the proper parent for plld_dsi	2015-04-10 16:04:22 +02:00
clk.c	clk: tegra: Add peripheral registers for bank Y	2015-04-10 16:04:20 +02:00
clk.h	clk: tegra: Model oscillator as clock	2015-04-10 16:04:20 +02:00
Makefile	clk: tegra: Add support for the Tegra132 CAR IP block	2015-02-02 15:47:53 +02:00