kernel-fxtec-pro1x/sound/soc
Ben Zhang 1aa844cd56 ASoC: rt5677: Reconfigure PLL1 after resume
Sometimes PLL1 stops working if the codec loses power
during suspend (when pow-ldo2 or reset gpio is used).
MX-7Bh(RT5677_PLL1_CTRL2) is cleared and won't be restored
by regcache since it's volatile. MX-7Bh has one status bit
and M code for PLL1. rt5677_set_dai_pll doesn't reconfigure
PLL1 after resume because it thinks the PLL params are not
changed.

This patch clears the cached PLL params at resume so that
rt5677_set_dai_pll can reconfigure the PLL after resume.

Signed-off-by: Ben Zhang <benzh@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-12-16 19:20:59 +00:00
..
adi
atmel
au1x
bcm
blackfin
cirrus
codecs ASoC: rt5677: Reconfigure PLL1 after resume 2015-12-16 19:20:59 +00:00
davinci
dwc
fsl
generic
intel
jz4740
kirkwood
mediatek
mxs
nuc900
omap
pxa
qcom
rockchip
samsung
sh
sirf
spear
sti
sunxi
tegra
txx9
ux500
xtensa
zte
Kconfig
Makefile
soc-ac97.c
soc-cache.c
soc-compress.c
soc-core.c
soc-dapm.c
soc-devres.c
soc-generic-dmaengine-pcm.c
soc-io.c
soc-jack.c
soc-ops.c
soc-pcm.c
soc-topology.c
soc-utils.c