d6a322774c
This round we have few new features, new driver and updates to few drivers.
The new features to dmaengine core are:
- Synchronized transfer termination API to terminate the dmaengine
transfers in synchronized and async fashion as required by users.
We have its user now in ALSA dmaengine lib, img, at_xdma, axi_dmac
drivers.
- Universal API for channel request and start consolidation of request
flows. It's user is ompa-dma driver.
- Introduce reuse of descriptors and use in pxa_dma driver
Add/Remove:
- STM32 DMA driver
- Removal of unused R-Car HPB-DMAC driver
Updates:
- ti-dma-crossbar updates for supporting eDMA
- tegra-apb pm updates
- idma64
- mv_xor updates
- ste_dma updates
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJWlO5UAAoJEHwUBw8lI4NH1OAP+QG35WZx3e2kfk7O4xKTugEg
i0vGdSxMu1ILKUsi+ZjwzGaMcheDDfBTRMzlBZNqYoFfnV1ull2re/GM+DwjCg6C
xuYDThhwghj+42CNRb5FGNHlLsNczNTsD3KfPAg9BjMOxEUW8bUQMtEp7cEhvf9F
+BoxTXInrEGeKeZRl557pBSSYfhs/y/b9etMY7JNKSk97C3isNHFRMV3cBESGmch
GaQR+3IEtbQfsuOypJpPMA2qmH/wQUeiQOgSR0EW9+599azVbUYohDTkBP1qA2aY
W0/UBybsCo+tFitB8WZTBAkMCmrHXqdub7sfo467oZvuJoqIIflWkr5fgLSI2tdA
+6EPIXNCjFfk5r3PrmcWBoeJ29S3/t9hRdfSvcWPX5+tdqqcD/qaLsYqMnb15bkj
sPAbhZcIb7OJRz2ibaTjcamyBXfqV89suRF64Fokm1/sN78IALtv/0RsHwEULmVJ
yZfRB8U9T7Or45FGODrfeQCIyKkJD0lCfTJryVHUdix+UgidZByuMW726B4E6V6R
tPB/tQCoHlZeUuWclR1BOpaZhtHmpMFZsBlZCHVU4GIwUkzWhlnt7FgOXPUY8gWf
zof9rMfPbZzykrlEi+iYLCPG8JCm0gzbcEeMRsr2rIBPmXW8ZRpW4+829wBgdDXs
vtJLlB8ZTlF2gaDWhDEt
=D5Fb
-----END PGP SIGNATURE-----
Merge tag 'dmaengine-4.5-rc1' of git://git.infradead.org/users/vkoul/slave-dma
Pull dmaengine updates from Vinod Koul:
"This round we have few new features, new driver and updates to few
drivers.
The new features to dmaengine core are:
- Synchronized transfer termination API to terminate the dmaengine
transfers in synchronized and async fashion as required by users.
We have its user now in ALSA dmaengine lib, img, at_xdma, axi_dmac
drivers.
- Universal API for channel request and start consolidation of
request flows. It's user is ompa-dma driver.
- Introduce reuse of descriptors and use in pxa_dma driver
Add/Remove:
- New STM32 DMA driver
- Removal of unused R-Car HPB-DMAC driver
Updates:
- ti-dma-crossbar updates for supporting eDMA
- tegra-apb pm updates
- idma64
- mv_xor updates
- ste_dma updates"
* tag 'dmaengine-4.5-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (54 commits)
dmaengine: mv_xor: add suspend/resume support
dmaengine: mv_xor: de-duplicate mv_chan_set_mode*()
dmaengine: mv_xor: remove mv_xor_chan->current_type field
dmaengine: omap-dma: Add support for DMA filter mapping to slave devices
dmaengine: edma: Add support for DMA filter mapping to slave devices
dmaengine: core: Introduce new, universal API to request a channel
dmaengine: core: Move and merge the code paths using private_candidate
dmaengine: core: Skip mask matching when it is not provided to private_candidate
dmaengine: mdc: Correct terminate_all handling
dmaengine: edma: Add probe callback to edma_tptc_driver
dmaengine: dw: fix potential memory leak in dw_dma_parse_dt()
dmaengine: stm32-dma: Fix unchecked deference of chan->desc
dmaengine: sh: Remove unused R-Car HPB-DMAC driver
dmaengine: usb-dmac: Document SoC specific compatibility strings
ste_dma40: Delete an unnecessary variable initialisation in d40_probe()
ste_dma40: Delete another unnecessary check in d40_probe()
ste_dma40: Delete an unnecessary check before the function call "kmem_cache_destroy"
dmaengine: tegra-apb: Free interrupts before killing tasklets
dmaengine: tegra-apb: Update driver to use GFP_NOWAIT
dmaengine: tegra-apb: Only save channel state for those in use
...
88 lines
2.7 KiB
C
88 lines
2.7 KiB
C
/*
|
|
* TI EDMA definitions
|
|
*
|
|
* Copyright (C) 2006-2013 Texas Instruments.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the
|
|
* Free Software Foundation; either version 2 of the License, or (at your
|
|
* option) any later version.
|
|
*/
|
|
|
|
/*
|
|
* This EDMA3 programming framework exposes two basic kinds of resource:
|
|
*
|
|
* Channel Triggers transfers, usually from a hardware event but
|
|
* also manually or by "chaining" from DMA completions.
|
|
* Each channel is coupled to a Parameter RAM (PaRAM) slot.
|
|
*
|
|
* Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
|
|
* "set"), source and destination addresses, a link to a
|
|
* next PaRAM slot (if any), options for the transfer, and
|
|
* instructions for updating those addresses. There are
|
|
* more than twice as many slots as event channels.
|
|
*
|
|
* Each PaRAM set describes a sequence of transfers, either for one large
|
|
* buffer or for several discontiguous smaller buffers. An EDMA transfer
|
|
* is driven only from a channel, which performs the transfers specified
|
|
* in its PaRAM slot until there are no more transfers. When that last
|
|
* transfer completes, the "link" field may be used to reload the channel's
|
|
* PaRAM slot with a new transfer descriptor.
|
|
*
|
|
* The EDMA Channel Controller (CC) maps requests from channels into physical
|
|
* Transfer Controller (TC) requests when the channel triggers (by hardware
|
|
* or software events, or by chaining). The two physical DMA channels provided
|
|
* by the TCs are thus shared by many logical channels.
|
|
*
|
|
* DaVinci hardware also has a "QDMA" mechanism which is not currently
|
|
* supported through this interface. (DSP firmware uses it though.)
|
|
*/
|
|
|
|
#ifndef EDMA_H_
|
|
#define EDMA_H_
|
|
|
|
enum dma_event_q {
|
|
EVENTQ_0 = 0,
|
|
EVENTQ_1 = 1,
|
|
EVENTQ_2 = 2,
|
|
EVENTQ_3 = 3,
|
|
EVENTQ_DEFAULT = -1
|
|
};
|
|
|
|
#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
|
|
#define EDMA_CTLR(i) ((i) >> 16)
|
|
#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
|
|
|
|
#define EDMA_FILTER_PARAM(ctlr, chan) ((int[]) { EDMA_CTLR_CHAN(ctlr, chan) })
|
|
|
|
struct edma_rsv_info {
|
|
|
|
const s16 (*rsv_chans)[2];
|
|
const s16 (*rsv_slots)[2];
|
|
};
|
|
|
|
struct dma_slave_map;
|
|
|
|
/* platform_data for EDMA driver */
|
|
struct edma_soc_info {
|
|
/*
|
|
* Default queue is expected to be a low-priority queue.
|
|
* This way, long transfers on the default queue started
|
|
* by the codec engine will not cause audio defects.
|
|
*/
|
|
enum dma_event_q default_queue;
|
|
|
|
/* Resource reservation for other cores */
|
|
struct edma_rsv_info *rsv;
|
|
|
|
/* List of channels allocated for memcpy, terminated with -1 */
|
|
s32 *memcpy_channels;
|
|
|
|
s8 (*queue_priority_mapping)[2];
|
|
const s16 (*xbar_chans)[2];
|
|
|
|
const struct dma_slave_map *slave_map;
|
|
int slavecnt;
|
|
};
|
|
|
|
#endif
|