7868f1ed84
Add new UV-specific header files. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
266 lines
10 KiB
C
266 lines
10 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI UV MMR definitions
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*
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* Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef __ASM_IA64_UV_MMRS__
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#define __ASM_IA64_UV_MMRS__
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/*
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* AUTO GENERATED - Do not edit
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*/
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#define UV_MMR_ENABLE (1UL << 63)
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/* ========================================================================= */
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/* UVH_NODE_ID */
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/* ========================================================================= */
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#define UVH_NODE_ID 0x0UL
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#define UVH_NODE_ID_FORCE1_SHFT 0
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#define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL
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#define UVH_NODE_ID_MANUFACTURER_SHFT 1
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#define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
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#define UVH_NODE_ID_PART_NUMBER_SHFT 12
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#define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
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#define UVH_NODE_ID_REVISION_SHFT 28
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#define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL
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#define UVH_NODE_ID_NODE_ID_SHFT 32
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#define UVH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
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#define UVH_NODE_ID_NODES_PER_BIT_SHFT 48
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#define UVH_NODE_ID_NODES_PER_BIT_MASK 0x007f000000000000UL
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#define UVH_NODE_ID_NI_PORT_SHFT 56
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#define UVH_NODE_ID_NI_PORT_MASK 0x0f00000000000000UL
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union uvh_node_id_u {
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unsigned long v;
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struct uvh_node_id_s {
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unsigned long force1 : 1; /* RO */
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unsigned long manufacturer : 11; /* RO */
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unsigned long part_number : 16; /* RO */
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unsigned long revision : 4; /* RO */
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unsigned long node_id : 15; /* RW */
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unsigned long rsvd_47 : 1; /* */
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unsigned long nodes_per_bit : 7; /* RW */
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unsigned long rsvd_55 : 1; /* */
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unsigned long ni_port : 4; /* RO */
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unsigned long rsvd_60_63 : 4; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
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union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
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unsigned long rsvd_0_23 : 24; /* */
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unsigned long dest_base : 22; /* RW */
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unsigned long rsvd_46_63: 18; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
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union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
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unsigned long rsvd_0_23 : 24; /* */
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unsigned long dest_base : 22; /* RW */
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unsigned long rsvd_46_63: 18; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
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#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
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union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
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unsigned long rsvd_0_23 : 24; /* */
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unsigned long dest_base : 22; /* RW */
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unsigned long rsvd_46_63: 18; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
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#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_gru_overlay_config_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_gru_overlay_config_mmr_s {
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unsigned long rsvd_0_27: 28; /* */
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unsigned long base : 18; /* RW */
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unsigned long gr4 : 1; /* RW */
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unsigned long rsvd_47_51: 5; /* */
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unsigned long n_gru : 4; /* RW */
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unsigned long rsvd_56_62: 7; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
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/* ========================================================================= */
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_SHFT 46
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_DUAL_HUB_MASK 0x0000400000000000UL
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
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#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
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union uvh_rh_gam_mmr_overlay_config_mmr_u {
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unsigned long v;
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struct uvh_rh_gam_mmr_overlay_config_mmr_s {
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unsigned long rsvd_0_25: 26; /* */
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unsigned long base : 20; /* RW */
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unsigned long dual_hub : 1; /* RW */
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unsigned long rsvd_47_62: 16; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_RTC */
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/* ========================================================================= */
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#define UVH_RTC 0x28000UL
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#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
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#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
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union uvh_rtc_u {
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unsigned long v;
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struct uvh_rtc_s {
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unsigned long real_time_clock : 56; /* RW */
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unsigned long rsvd_56_63 : 8; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ADDR_MAP_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
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#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_SHFT 0
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#define UVH_SI_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL
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#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_SHFT 8
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#define UVH_SI_ADDR_MAP_CONFIG_N_SKT_MASK 0x0000000000000f00UL
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union uvh_si_addr_map_config_u {
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unsigned long v;
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struct uvh_si_addr_map_config_s {
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unsigned long m_skt : 6; /* RW */
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unsigned long rsvd_6_7: 2; /* */
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unsigned long n_skt : 4; /* RW */
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unsigned long rsvd_12_63: 52; /* */
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
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#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
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union uvh_si_alias0_overlay_config_u {
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unsigned long v;
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struct uvh_si_alias0_overlay_config_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
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#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
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union uvh_si_alias1_overlay_config_u {
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unsigned long v;
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struct uvh_si_alias1_overlay_config_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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/* ========================================================================= */
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/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
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/* ========================================================================= */
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
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#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
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union uvh_si_alias2_overlay_config_u {
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unsigned long v;
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struct uvh_si_alias2_overlay_config_s {
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unsigned long rsvd_0_23: 24; /* */
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unsigned long base : 8; /* RW */
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unsigned long rsvd_32_47: 16; /* */
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unsigned long m_alias : 5; /* RW */
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unsigned long rsvd_53_62: 10; /* */
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unsigned long enable : 1; /* RW */
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} s;
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};
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#endif /* __ASM_IA64_UV_MMRS__ */
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