1965aae3c9
Change header guards named "ASM_X86__*" to "_ASM_X86_*" since: a. the double underscore is ugly and pointless. b. no leading underscore violates namespace constraints. Signed-off-by: H. Peter Anvin <hpa@zytor.com>
107 lines
2.6 KiB
C
107 lines
2.6 KiB
C
#ifndef _ASM_X86_VISWS__PIIX4_H
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#define _ASM_X86_VISWS__PIIX4_H
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/*
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* PIIX4 as used on SGI Visual Workstations
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*/
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#define PIIX_PM_START 0x0F80
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#define SIO_GPIO_START 0x0FC0
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#define SIO_PM_START 0x0FC8
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#define PMBASE PIIX_PM_START
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#define GPIREG0 (PMBASE+0x30)
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#define GPIREG(x) (GPIREG0+((x)/8))
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#define GPIBIT(x) (1 << ((x)%8))
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#define PIIX_GPI_BD_ID1 18
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#define PIIX_GPI_BD_ID2 19
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#define PIIX_GPI_BD_ID3 20
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#define PIIX_GPI_BD_ID4 21
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#define PIIX_GPI_BD_REG GPIREG(PIIX_GPI_BD_ID1)
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#define PIIX_GPI_BD_MASK (GPIBIT(PIIX_GPI_BD_ID1) | \
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GPIBIT(PIIX_GPI_BD_ID2) | \
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GPIBIT(PIIX_GPI_BD_ID3) | \
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GPIBIT(PIIX_GPI_BD_ID4) )
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#define PIIX_GPI_BD_SHIFT (PIIX_GPI_BD_ID1 % 8)
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#define SIO_INDEX 0x2e
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#define SIO_DATA 0x2f
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#define SIO_DEV_SEL 0x7
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#define SIO_DEV_ENB 0x30
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#define SIO_DEV_MSB 0x60
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#define SIO_DEV_LSB 0x61
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#define SIO_GP_DEV 0x7
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#define SIO_GP_BASE SIO_GPIO_START
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#define SIO_GP_MSB (SIO_GP_BASE>>8)
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#define SIO_GP_LSB (SIO_GP_BASE&0xff)
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#define SIO_GP_DATA1 (SIO_GP_BASE+0)
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#define SIO_PM_DEV 0x8
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#define SIO_PM_BASE SIO_PM_START
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#define SIO_PM_MSB (SIO_PM_BASE>>8)
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#define SIO_PM_LSB (SIO_PM_BASE&0xff)
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#define SIO_PM_INDEX (SIO_PM_BASE+0)
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#define SIO_PM_DATA (SIO_PM_BASE+1)
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#define SIO_PM_FER2 0x1
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#define SIO_PM_GP_EN 0x80
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/*
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* This is the dev/reg where generating a config cycle will
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* result in a PCI special cycle.
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*/
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#define SPECIAL_DEV 0xff
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#define SPECIAL_REG 0x00
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/*
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* PIIX4 needs to see a special cycle with the following data
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* to be convinced the processor has gone into the stop grant
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* state. PIIX4 insists on seeing this before it will power
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* down a system.
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*/
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#define PIIX_SPECIAL_STOP 0x00120002
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#define PIIX4_RESET_PORT 0xcf9
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#define PIIX4_RESET_VAL 0x6
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#define PMSTS_PORT 0xf80 // 2 bytes PM Status
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#define PMEN_PORT 0xf82 // 2 bytes PM Enable
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#define PMCNTRL_PORT 0xf84 // 2 bytes PM Control
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#define PM_SUSPEND_ENABLE 0x2000 // start sequence to suspend state
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/*
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* PMSTS and PMEN I/O bit definitions.
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* (Bits are the same in both registers)
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*/
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#define PM_STS_RSM (1<<15) // Resume Status
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#define PM_STS_PWRBTNOR (1<<11) // Power Button Override
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#define PM_STS_RTC (1<<10) // RTC status
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#define PM_STS_PWRBTN (1<<8) // Power Button Pressed?
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#define PM_STS_GBL (1<<5) // Global Status
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#define PM_STS_BM (1<<4) // Bus Master Status
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#define PM_STS_TMROF (1<<0) // Timer Overflow Status.
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/*
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* Stop clock GPI register
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*/
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#define PIIX_GPIREG0 (0xf80 + 0x30)
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/*
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* Stop clock GPI bit in GPIREG0
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*/
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#define PIIX_GPI_STPCLK 0x4 // STPCLK signal routed back in
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#endif /* _ASM_X86_VISWS__PIIX4_H */
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