5bbc097d89
This patch disables GartTlbWlk errors on AMD Fam10h CPUs if the BIOS forgets to do is (or is just too old). Letting these errors enabled can cause a sync-flood on the CPU causing a reboot. The AMD BKDG recommends disabling GART TLB Wlk Error completely. This patch is the fix for https://bugzilla.kernel.org/show_bug.cgi?id=33012 on my machine. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Link: http://lkml.kernel.org/r/20110415131152.GJ18463@8bytes.org Tested-by: Alexandre Demers <alexandre.f.demers@gmail.com> Cc: <stable@kernel.org> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
447 lines
16 KiB
C
447 lines
16 KiB
C
#ifndef _ASM_X86_MSR_INDEX_H
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#define _ASM_X86_MSR_INDEX_H
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/* CPU model specific register (MSR) numbers */
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/* x86-64 specific MSRs */
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#define MSR_EFER 0xc0000080 /* extended feature register */
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#define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
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#define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
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#define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target */
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#define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
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#define MSR_FS_BASE 0xc0000100 /* 64bit FS base */
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#define MSR_GS_BASE 0xc0000101 /* 64bit GS base */
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#define MSR_KERNEL_GS_BASE 0xc0000102 /* SwapGS GS shadow */
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#define MSR_TSC_AUX 0xc0000103 /* Auxiliary TSC */
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/* EFER bits: */
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#define _EFER_SCE 0 /* SYSCALL/SYSRET */
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#define _EFER_LME 8 /* Long mode enable */
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#define _EFER_LMA 10 /* Long mode active (read-only) */
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#define _EFER_NX 11 /* No execute enable */
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#define _EFER_SVME 12 /* Enable virtualization */
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#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
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#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
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#define EFER_SCE (1<<_EFER_SCE)
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#define EFER_LME (1<<_EFER_LME)
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#define EFER_LMA (1<<_EFER_LMA)
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#define EFER_NX (1<<_EFER_NX)
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#define EFER_SVME (1<<_EFER_SVME)
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#define EFER_LMSLE (1<<_EFER_LMSLE)
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#define EFER_FFXSR (1<<_EFER_FFXSR)
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/* Intel MSRs. Some also available on other CPUs */
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#define MSR_IA32_PERFCTR0 0x000000c1
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#define MSR_IA32_PERFCTR1 0x000000c2
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#define MSR_FSB_FREQ 0x000000cd
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#define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
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#define NHM_C3_AUTO_DEMOTE (1UL << 25)
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#define NHM_C1_AUTO_DEMOTE (1UL << 26)
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#define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25)
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#define MSR_MTRRcap 0x000000fe
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#define MSR_IA32_BBL_CR_CTL 0x00000119
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#define MSR_IA32_BBL_CR_CTL3 0x0000011e
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#define MSR_IA32_SYSENTER_CS 0x00000174
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#define MSR_IA32_SYSENTER_ESP 0x00000175
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#define MSR_IA32_SYSENTER_EIP 0x00000176
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#define MSR_IA32_MCG_CAP 0x00000179
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#define MSR_IA32_MCG_STATUS 0x0000017a
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#define MSR_IA32_MCG_CTL 0x0000017b
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#define MSR_OFFCORE_RSP_0 0x000001a6
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#define MSR_OFFCORE_RSP_1 0x000001a7
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#define MSR_IA32_PEBS_ENABLE 0x000003f1
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#define MSR_IA32_DS_AREA 0x00000600
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#define MSR_IA32_PERF_CAPABILITIES 0x00000345
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#define MSR_MTRRfix64K_00000 0x00000250
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#define MSR_MTRRfix16K_80000 0x00000258
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#define MSR_MTRRfix16K_A0000 0x00000259
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#define MSR_MTRRfix4K_C0000 0x00000268
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#define MSR_MTRRfix4K_C8000 0x00000269
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#define MSR_MTRRfix4K_D0000 0x0000026a
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#define MSR_MTRRfix4K_D8000 0x0000026b
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#define MSR_MTRRfix4K_E0000 0x0000026c
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#define MSR_MTRRfix4K_E8000 0x0000026d
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#define MSR_MTRRfix4K_F0000 0x0000026e
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#define MSR_MTRRfix4K_F8000 0x0000026f
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#define MSR_MTRRdefType 0x000002ff
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#define MSR_IA32_CR_PAT 0x00000277
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#define MSR_IA32_DEBUGCTLMSR 0x000001d9
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#define MSR_IA32_LASTBRANCHFROMIP 0x000001db
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#define MSR_IA32_LASTBRANCHTOIP 0x000001dc
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#define MSR_IA32_LASTINTFROMIP 0x000001dd
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#define MSR_IA32_LASTINTTOIP 0x000001de
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/* DEBUGCTLMSR bits (others vary by model): */
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#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
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#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
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#define DEBUGCTLMSR_TR (1UL << 6)
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#define DEBUGCTLMSR_BTS (1UL << 7)
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#define DEBUGCTLMSR_BTINT (1UL << 8)
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#define DEBUGCTLMSR_BTS_OFF_OS (1UL << 9)
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#define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10)
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#define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11)
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#define MSR_IA32_MC0_CTL 0x00000400
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#define MSR_IA32_MC0_STATUS 0x00000401
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#define MSR_IA32_MC0_ADDR 0x00000402
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#define MSR_IA32_MC0_MISC 0x00000403
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#define MSR_AMD64_MC0_MASK 0xc0010044
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#define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x))
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#define MSR_IA32_MCx_STATUS(x) (MSR_IA32_MC0_STATUS + 4*(x))
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#define MSR_IA32_MCx_ADDR(x) (MSR_IA32_MC0_ADDR + 4*(x))
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#define MSR_IA32_MCx_MISC(x) (MSR_IA32_MC0_MISC + 4*(x))
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#define MSR_AMD64_MCx_MASK(x) (MSR_AMD64_MC0_MASK + (x))
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/* These are consecutive and not in the normal 4er MCE bank block */
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#define MSR_IA32_MC0_CTL2 0x00000280
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#define MSR_IA32_MCx_CTL2(x) (MSR_IA32_MC0_CTL2 + (x))
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#define MSR_P6_PERFCTR0 0x000000c1
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#define MSR_P6_PERFCTR1 0x000000c2
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#define MSR_P6_EVNTSEL0 0x00000186
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#define MSR_P6_EVNTSEL1 0x00000187
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/* AMD64 MSRs. Not complete. See the architecture manual for a more
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complete list. */
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#define MSR_AMD64_PATCH_LEVEL 0x0000008b
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#define MSR_AMD64_NB_CFG 0xc001001f
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#define MSR_AMD64_PATCH_LOADER 0xc0010020
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#define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140
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#define MSR_AMD64_OSVW_STATUS 0xc0010141
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#define MSR_AMD64_DC_CFG 0xc0011022
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#define MSR_AMD64_IBSFETCHCTL 0xc0011030
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#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
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#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
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#define MSR_AMD64_IBSOPCTL 0xc0011033
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#define MSR_AMD64_IBSOPRIP 0xc0011034
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#define MSR_AMD64_IBSOPDATA 0xc0011035
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#define MSR_AMD64_IBSOPDATA2 0xc0011036
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#define MSR_AMD64_IBSOPDATA3 0xc0011037
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#define MSR_AMD64_IBSDCLINAD 0xc0011038
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#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
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#define MSR_AMD64_IBSCTL 0xc001103a
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#define MSR_AMD64_IBSBRTARGET 0xc001103b
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/* Fam 15h MSRs */
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#define MSR_F15H_PERF_CTL 0xc0010200
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#define MSR_F15H_PERF_CTR 0xc0010201
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/* Fam 10h MSRs */
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#define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058
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#define FAM10H_MMIO_CONF_ENABLE (1<<0)
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#define FAM10H_MMIO_CONF_BUSRANGE_MASK 0xf
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#define FAM10H_MMIO_CONF_BUSRANGE_SHIFT 2
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#define FAM10H_MMIO_CONF_BASE_MASK 0xfffffffULL
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#define FAM10H_MMIO_CONF_BASE_SHIFT 20
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#define MSR_FAM10H_NODE_ID 0xc001100c
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/* K8 MSRs */
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#define MSR_K8_TOP_MEM1 0xc001001a
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#define MSR_K8_TOP_MEM2 0xc001001d
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#define MSR_K8_SYSCFG 0xc0010010
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#define MSR_K8_INT_PENDING_MSG 0xc0010055
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/* C1E active bits in int pending message */
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#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
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#define MSR_K8_TSEG_ADDR 0xc0010112
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#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
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#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
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#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
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/* K7 MSRs */
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#define MSR_K7_EVNTSEL0 0xc0010000
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#define MSR_K7_PERFCTR0 0xc0010004
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#define MSR_K7_EVNTSEL1 0xc0010001
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#define MSR_K7_PERFCTR1 0xc0010005
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#define MSR_K7_EVNTSEL2 0xc0010002
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#define MSR_K7_PERFCTR2 0xc0010006
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#define MSR_K7_EVNTSEL3 0xc0010003
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#define MSR_K7_PERFCTR3 0xc0010007
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#define MSR_K7_CLK_CTL 0xc001001b
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#define MSR_K7_HWCR 0xc0010015
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#define MSR_K7_FID_VID_CTL 0xc0010041
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#define MSR_K7_FID_VID_STATUS 0xc0010042
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/* K6 MSRs */
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#define MSR_K6_WHCR 0xc0000082
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#define MSR_K6_UWCCR 0xc0000085
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#define MSR_K6_EPMR 0xc0000086
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#define MSR_K6_PSOR 0xc0000087
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#define MSR_K6_PFIR 0xc0000088
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/* Centaur-Hauls/IDT defined MSRs. */
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#define MSR_IDT_FCR1 0x00000107
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#define MSR_IDT_FCR2 0x00000108
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#define MSR_IDT_FCR3 0x00000109
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#define MSR_IDT_FCR4 0x0000010a
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#define MSR_IDT_MCR0 0x00000110
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#define MSR_IDT_MCR1 0x00000111
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#define MSR_IDT_MCR2 0x00000112
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#define MSR_IDT_MCR3 0x00000113
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#define MSR_IDT_MCR4 0x00000114
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#define MSR_IDT_MCR5 0x00000115
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#define MSR_IDT_MCR6 0x00000116
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#define MSR_IDT_MCR7 0x00000117
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#define MSR_IDT_MCR_CTRL 0x00000120
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/* VIA Cyrix defined MSRs*/
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#define MSR_VIA_FCR 0x00001107
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#define MSR_VIA_LONGHAUL 0x0000110a
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#define MSR_VIA_RNG 0x0000110b
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#define MSR_VIA_BCR2 0x00001147
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/* Transmeta defined MSRs */
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#define MSR_TMTA_LONGRUN_CTRL 0x80868010
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#define MSR_TMTA_LONGRUN_FLAGS 0x80868011
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#define MSR_TMTA_LRTI_READOUT 0x80868018
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#define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
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/* Intel defined MSRs. */
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#define MSR_IA32_P5_MC_ADDR 0x00000000
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#define MSR_IA32_P5_MC_TYPE 0x00000001
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#define MSR_IA32_TSC 0x00000010
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#define MSR_IA32_PLATFORM_ID 0x00000017
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#define MSR_IA32_EBL_CR_POWERON 0x0000002a
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#define MSR_EBC_FREQUENCY_ID 0x0000002c
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#define MSR_IA32_FEATURE_CONTROL 0x0000003a
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#define FEATURE_CONTROL_LOCKED (1<<0)
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#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1)
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#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
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#define MSR_IA32_APICBASE 0x0000001b
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#define MSR_IA32_APICBASE_BSP (1<<8)
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#define MSR_IA32_APICBASE_ENABLE (1<<11)
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#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
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#define MSR_IA32_UCODE_WRITE 0x00000079
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#define MSR_IA32_UCODE_REV 0x0000008b
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#define MSR_IA32_PERF_STATUS 0x00000198
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#define MSR_IA32_PERF_CTL 0x00000199
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#define MSR_IA32_MPERF 0x000000e7
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#define MSR_IA32_APERF 0x000000e8
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#define MSR_IA32_THERM_CONTROL 0x0000019a
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#define MSR_IA32_THERM_INTERRUPT 0x0000019b
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#define THERM_INT_HIGH_ENABLE (1 << 0)
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#define THERM_INT_LOW_ENABLE (1 << 1)
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#define THERM_INT_PLN_ENABLE (1 << 24)
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#define MSR_IA32_THERM_STATUS 0x0000019c
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#define THERM_STATUS_PROCHOT (1 << 0)
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#define THERM_STATUS_POWER_LIMIT (1 << 10)
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#define MSR_THERM2_CTL 0x0000019d
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#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
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#define MSR_IA32_MISC_ENABLE 0x000001a0
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#define MSR_IA32_TEMPERATURE_TARGET 0x000001a2
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#define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
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#define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1
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#define PACKAGE_THERM_STATUS_PROCHOT (1 << 0)
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#define PACKAGE_THERM_STATUS_POWER_LIMIT (1 << 10)
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#define MSR_IA32_PACKAGE_THERM_INTERRUPT 0x000001b2
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#define PACKAGE_THERM_INT_HIGH_ENABLE (1 << 0)
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#define PACKAGE_THERM_INT_LOW_ENABLE (1 << 1)
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#define PACKAGE_THERM_INT_PLN_ENABLE (1 << 24)
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/* Thermal Thresholds Support */
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#define THERM_INT_THRESHOLD0_ENABLE (1 << 15)
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#define THERM_SHIFT_THRESHOLD0 8
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#define THERM_MASK_THRESHOLD0 (0x7f << THERM_SHIFT_THRESHOLD0)
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#define THERM_INT_THRESHOLD1_ENABLE (1 << 23)
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#define THERM_SHIFT_THRESHOLD1 16
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#define THERM_MASK_THRESHOLD1 (0x7f << THERM_SHIFT_THRESHOLD1)
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#define THERM_STATUS_THRESHOLD0 (1 << 6)
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#define THERM_LOG_THRESHOLD0 (1 << 7)
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#define THERM_STATUS_THRESHOLD1 (1 << 8)
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#define THERM_LOG_THRESHOLD1 (1 << 9)
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/* MISC_ENABLE bits: architectural */
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#define MSR_IA32_MISC_ENABLE_FAST_STRING (1ULL << 0)
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#define MSR_IA32_MISC_ENABLE_TCC (1ULL << 1)
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#define MSR_IA32_MISC_ENABLE_EMON (1ULL << 7)
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#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1ULL << 11)
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#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1ULL << 12)
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#define MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP (1ULL << 16)
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#define MSR_IA32_MISC_ENABLE_MWAIT (1ULL << 18)
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#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID (1ULL << 22)
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#define MSR_IA32_MISC_ENABLE_XTPR_DISABLE (1ULL << 23)
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#define MSR_IA32_MISC_ENABLE_XD_DISABLE (1ULL << 34)
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/* MISC_ENABLE bits: model-specific, meaning may vary from core to core */
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#define MSR_IA32_MISC_ENABLE_X87_COMPAT (1ULL << 2)
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#define MSR_IA32_MISC_ENABLE_TM1 (1ULL << 3)
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#define MSR_IA32_MISC_ENABLE_SPLIT_LOCK_DISABLE (1ULL << 4)
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#define MSR_IA32_MISC_ENABLE_L3CACHE_DISABLE (1ULL << 6)
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#define MSR_IA32_MISC_ENABLE_SUPPRESS_LOCK (1ULL << 8)
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#define MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE (1ULL << 9)
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#define MSR_IA32_MISC_ENABLE_FERR (1ULL << 10)
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#define MSR_IA32_MISC_ENABLE_FERR_MULTIPLEX (1ULL << 10)
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#define MSR_IA32_MISC_ENABLE_TM2 (1ULL << 13)
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#define MSR_IA32_MISC_ENABLE_ADJ_PREF_DISABLE (1ULL << 19)
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#define MSR_IA32_MISC_ENABLE_SPEEDSTEP_LOCK (1ULL << 20)
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#define MSR_IA32_MISC_ENABLE_L1D_CONTEXT (1ULL << 24)
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#define MSR_IA32_MISC_ENABLE_DCU_PREF_DISABLE (1ULL << 37)
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#define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38)
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#define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39)
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/* P4/Xeon+ specific */
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#define MSR_IA32_MCG_EAX 0x00000180
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#define MSR_IA32_MCG_EBX 0x00000181
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#define MSR_IA32_MCG_ECX 0x00000182
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#define MSR_IA32_MCG_EDX 0x00000183
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#define MSR_IA32_MCG_ESI 0x00000184
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#define MSR_IA32_MCG_EDI 0x00000185
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#define MSR_IA32_MCG_EBP 0x00000186
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#define MSR_IA32_MCG_ESP 0x00000187
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#define MSR_IA32_MCG_EFLAGS 0x00000188
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#define MSR_IA32_MCG_EIP 0x00000189
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#define MSR_IA32_MCG_RESERVED 0x0000018a
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/* Pentium IV performance counter MSRs */
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#define MSR_P4_BPU_PERFCTR0 0x00000300
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#define MSR_P4_BPU_PERFCTR1 0x00000301
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#define MSR_P4_BPU_PERFCTR2 0x00000302
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#define MSR_P4_BPU_PERFCTR3 0x00000303
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#define MSR_P4_MS_PERFCTR0 0x00000304
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#define MSR_P4_MS_PERFCTR1 0x00000305
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#define MSR_P4_MS_PERFCTR2 0x00000306
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#define MSR_P4_MS_PERFCTR3 0x00000307
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#define MSR_P4_FLAME_PERFCTR0 0x00000308
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#define MSR_P4_FLAME_PERFCTR1 0x00000309
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#define MSR_P4_FLAME_PERFCTR2 0x0000030a
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#define MSR_P4_FLAME_PERFCTR3 0x0000030b
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#define MSR_P4_IQ_PERFCTR0 0x0000030c
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#define MSR_P4_IQ_PERFCTR1 0x0000030d
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#define MSR_P4_IQ_PERFCTR2 0x0000030e
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#define MSR_P4_IQ_PERFCTR3 0x0000030f
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#define MSR_P4_IQ_PERFCTR4 0x00000310
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#define MSR_P4_IQ_PERFCTR5 0x00000311
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#define MSR_P4_BPU_CCCR0 0x00000360
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#define MSR_P4_BPU_CCCR1 0x00000361
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#define MSR_P4_BPU_CCCR2 0x00000362
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#define MSR_P4_BPU_CCCR3 0x00000363
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#define MSR_P4_MS_CCCR0 0x00000364
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#define MSR_P4_MS_CCCR1 0x00000365
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#define MSR_P4_MS_CCCR2 0x00000366
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#define MSR_P4_MS_CCCR3 0x00000367
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#define MSR_P4_FLAME_CCCR0 0x00000368
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#define MSR_P4_FLAME_CCCR1 0x00000369
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#define MSR_P4_FLAME_CCCR2 0x0000036a
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#define MSR_P4_FLAME_CCCR3 0x0000036b
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#define MSR_P4_IQ_CCCR0 0x0000036c
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#define MSR_P4_IQ_CCCR1 0x0000036d
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#define MSR_P4_IQ_CCCR2 0x0000036e
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#define MSR_P4_IQ_CCCR3 0x0000036f
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#define MSR_P4_IQ_CCCR4 0x00000370
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#define MSR_P4_IQ_CCCR5 0x00000371
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#define MSR_P4_ALF_ESCR0 0x000003ca
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#define MSR_P4_ALF_ESCR1 0x000003cb
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#define MSR_P4_BPU_ESCR0 0x000003b2
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#define MSR_P4_BPU_ESCR1 0x000003b3
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#define MSR_P4_BSU_ESCR0 0x000003a0
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#define MSR_P4_BSU_ESCR1 0x000003a1
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#define MSR_P4_CRU_ESCR0 0x000003b8
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#define MSR_P4_CRU_ESCR1 0x000003b9
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#define MSR_P4_CRU_ESCR2 0x000003cc
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#define MSR_P4_CRU_ESCR3 0x000003cd
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#define MSR_P4_CRU_ESCR4 0x000003e0
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#define MSR_P4_CRU_ESCR5 0x000003e1
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#define MSR_P4_DAC_ESCR0 0x000003a8
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#define MSR_P4_DAC_ESCR1 0x000003a9
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#define MSR_P4_FIRM_ESCR0 0x000003a4
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#define MSR_P4_FIRM_ESCR1 0x000003a5
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#define MSR_P4_FLAME_ESCR0 0x000003a6
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#define MSR_P4_FLAME_ESCR1 0x000003a7
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#define MSR_P4_FSB_ESCR0 0x000003a2
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#define MSR_P4_FSB_ESCR1 0x000003a3
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#define MSR_P4_IQ_ESCR0 0x000003ba
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#define MSR_P4_IQ_ESCR1 0x000003bb
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#define MSR_P4_IS_ESCR0 0x000003b4
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#define MSR_P4_IS_ESCR1 0x000003b5
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#define MSR_P4_ITLB_ESCR0 0x000003b6
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#define MSR_P4_ITLB_ESCR1 0x000003b7
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#define MSR_P4_IX_ESCR0 0x000003c8
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#define MSR_P4_IX_ESCR1 0x000003c9
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#define MSR_P4_MOB_ESCR0 0x000003aa
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#define MSR_P4_MOB_ESCR1 0x000003ab
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#define MSR_P4_MS_ESCR0 0x000003c0
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#define MSR_P4_MS_ESCR1 0x000003c1
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#define MSR_P4_PMH_ESCR0 0x000003ac
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#define MSR_P4_PMH_ESCR1 0x000003ad
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#define MSR_P4_RAT_ESCR0 0x000003bc
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#define MSR_P4_RAT_ESCR1 0x000003bd
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#define MSR_P4_SAAT_ESCR0 0x000003ae
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#define MSR_P4_SAAT_ESCR1 0x000003af
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#define MSR_P4_SSU_ESCR0 0x000003be
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#define MSR_P4_SSU_ESCR1 0x000003bf /* guess: not in manual */
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#define MSR_P4_TBPU_ESCR0 0x000003c2
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#define MSR_P4_TBPU_ESCR1 0x000003c3
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#define MSR_P4_TC_ESCR0 0x000003c4
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#define MSR_P4_TC_ESCR1 0x000003c5
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#define MSR_P4_U2L_ESCR0 0x000003b0
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#define MSR_P4_U2L_ESCR1 0x000003b1
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#define MSR_P4_PEBS_MATRIX_VERT 0x000003f2
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/* Intel Core-based CPU performance counters */
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#define MSR_CORE_PERF_FIXED_CTR0 0x00000309
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#define MSR_CORE_PERF_FIXED_CTR1 0x0000030a
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#define MSR_CORE_PERF_FIXED_CTR2 0x0000030b
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#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x0000038d
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#define MSR_CORE_PERF_GLOBAL_STATUS 0x0000038e
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#define MSR_CORE_PERF_GLOBAL_CTRL 0x0000038f
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#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x00000390
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/* Geode defined MSRs */
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#define MSR_GEODE_BUSCONT_CONF0 0x00001900
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/* Intel VT MSRs */
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#define MSR_IA32_VMX_BASIC 0x00000480
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#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
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#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
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#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
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#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
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#define MSR_IA32_VMX_MISC 0x00000485
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#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
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#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
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#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
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#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
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#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
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#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
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#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
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/* AMD-V MSRs */
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#define MSR_VM_CR 0xc0010114
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#define MSR_VM_IGNNE 0xc0010115
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#define MSR_VM_HSAVE_PA 0xc0010117
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#endif /* _ASM_X86_MSR_INDEX_H */
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