1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
541 lines
14 KiB
C
541 lines
14 KiB
C
/*
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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* Copyright (C) 2003, 2004 Paul Mundt
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* Copyright (C) 2004 Richard Curnow
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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* Support functions for the SH5 PCI hardware.
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/rwsem.h>
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#include <linux/smp.h>
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#include <linux/smp_lock.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/types.h>
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#include <asm/pci.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <asm/hardware.h>
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#include "pci_sh5.h"
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static unsigned long pcicr_virt;
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unsigned long pciio_virt;
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static void __init pci_fixup_ide_bases(struct pci_dev *d)
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{
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int i;
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/*
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* PCI IDE controllers use non-standard I/O port decoding, respect it.
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*/
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if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
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return;
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printk("PCI: IDE base address fixup for %s\n", pci_name(d));
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for(i=0; i<4; i++) {
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struct resource *r = &d->resource[i];
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if ((r->start & ~0x80) == 0x374) {
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r->start |= 2;
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r->end = r->start;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
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char * __init pcibios_setup(char *str)
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{
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return str;
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}
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/* Rounds a number UP to the nearest power of two. Used for
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* sizing the PCI window.
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*/
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static u32 __init r2p2(u32 num)
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{
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int i = 31;
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u32 tmp = num;
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if (num == 0)
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return 0;
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do {
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if (tmp & (1 << 31))
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break;
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i--;
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tmp <<= 1;
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} while (i >= 0);
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tmp = 1 << i;
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/* If the original number isn't a power of 2, round it up */
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if (tmp != num)
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tmp <<= 1;
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return tmp;
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}
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extern unsigned long long memory_start, memory_end;
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int __init sh5pci_init(unsigned memStart, unsigned memSize)
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{
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u32 lsr0;
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u32 uval;
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pcicr_virt = onchip_remap(SH5PCI_ICR_BASE, 1024, "PCICR");
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if (!pcicr_virt) {
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panic("Unable to remap PCICR\n");
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}
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pciio_virt = onchip_remap(SH5PCI_IO_BASE, 0x10000, "PCIIO");
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if (!pciio_virt) {
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panic("Unable to remap PCIIO\n");
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}
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pr_debug("Register base addres is 0x%08lx\n", pcicr_virt);
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/* Clear snoop registers */
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SH5PCI_WRITE(CSCR0, 0);
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SH5PCI_WRITE(CSCR1, 0);
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pr_debug("Wrote to reg\n");
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/* Switch off interrupts */
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SH5PCI_WRITE(INTM, 0);
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SH5PCI_WRITE(AINTM, 0);
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SH5PCI_WRITE(PINTM, 0);
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/* Set bus active, take it out of reset */
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uval = SH5PCI_READ(CR);
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/* Set command Register */
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SH5PCI_WRITE(CR, uval | CR_LOCK_MASK | CR_CFINT| CR_FTO | CR_PFE | CR_PFCS | CR_BMAM);
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uval=SH5PCI_READ(CR);
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pr_debug("CR is actually 0x%08x\n",uval);
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/* Allow it to be a master */
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/* NB - WE DISABLE I/O ACCESS to stop overlap */
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/* set WAIT bit to enable stepping, an attempt to improve stability */
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SH5PCI_WRITE_SHORT(CSR_CMD,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_WAIT);
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/*
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** Set translation mapping memory in order to convert the address
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** used for the main bus, to the PCI internal address.
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*/
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SH5PCI_WRITE(MBR,0x40000000);
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/* Always set the max size 512M */
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SH5PCI_WRITE(MBMR, PCISH5_MEM_SIZCONV(512*1024*1024));
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/*
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** I/O addresses are mapped at internal PCI specific address
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** as is described into the configuration bridge table.
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** These are changed to 0, to allow cards that have legacy
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** io such as vga to function correctly. We set the SH5 IOBAR to
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** 256K, which is a bit big as we can only have 64K of address space
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*/
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SH5PCI_WRITE(IOBR,0x0);
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pr_debug("PCI:Writing 0x%08x to IOBR\n",0);
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/* Set up a 256K window. Totally pointless waste of address space */
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SH5PCI_WRITE(IOBMR,0);
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pr_debug("PCI:Writing 0x%08x to IOBMR\n",0);
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/* The SH5 has a HUGE 256K I/O region, which breaks the PCI spec. Ideally,
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* we would want to map the I/O region somewhere, but it is so big this is not
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* that easy!
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*/
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SH5PCI_WRITE(CSR_IBAR0,~0);
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/* Set memory size value */
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memSize = memory_end - memory_start;
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/* Now we set up the mbars so the PCI bus can see the memory of the machine */
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if (memSize < (1024 * 1024)) {
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printk(KERN_ERR "PCISH5: Ridiculous memory size of 0x%x?\n", memSize);
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return -EINVAL;
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}
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/* Set LSR 0 */
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lsr0 = (memSize > (512 * 1024 * 1024)) ? 0x1ff00001 : ((r2p2(memSize) - 0x100000) | 0x1);
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SH5PCI_WRITE(LSR0, lsr0);
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pr_debug("PCI:Writing 0x%08x to LSR0\n",lsr0);
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/* Set MBAR 0 */
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SH5PCI_WRITE(CSR_MBAR0, memory_start);
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SH5PCI_WRITE(LAR0, memory_start);
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SH5PCI_WRITE(CSR_MBAR1,0);
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SH5PCI_WRITE(LAR1,0);
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SH5PCI_WRITE(LSR1,0);
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pr_debug("PCI:Writing 0x%08llx to CSR_MBAR0\n",memory_start);
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pr_debug("PCI:Writing 0x%08llx to LAR0\n",memory_start);
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/* Enable the PCI interrupts on the device */
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SH5PCI_WRITE(INTM, ~0);
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SH5PCI_WRITE(AINTM, ~0);
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SH5PCI_WRITE(PINTM, ~0);
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pr_debug("Switching on all error interrupts\n");
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return(0);
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}
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static int sh5pci_read(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *val)
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{
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SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
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switch (size) {
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case 1:
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*val = (u8)SH5PCI_READ_BYTE(PDR + (where & 3));
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break;
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case 2:
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*val = (u16)SH5PCI_READ_SHORT(PDR + (where & 2));
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break;
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case 4:
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*val = SH5PCI_READ(PDR);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int sh5pci_write(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 val)
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{
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SH5PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
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switch (size) {
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case 1:
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SH5PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
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break;
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case 2:
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SH5PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
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break;
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case 4:
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SH5PCI_WRITE(PDR, val);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops pci_config_ops = {
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.read = sh5pci_read,
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.write = sh5pci_write,
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};
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/* Everything hangs off this */
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static struct pci_bus *pci_root_bus;
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static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin)
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{
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pr_debug("swizzle for dev %d on bus %d slot %d pin is %d\n",
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dev->devfn,dev->bus->number, PCI_SLOT(dev->devfn),*pin);
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return PCI_SLOT(dev->devfn);
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}
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static inline u8 bridge_swizzle(u8 pin, u8 slot)
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{
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return (((pin-1) + slot) % 4) + 1;
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}
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u8 __init common_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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if (dev->bus->number != 0) {
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u8 pin = *pinp;
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do {
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pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
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/* Move up the chain of bridges. */
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dev = dev->bus->self;
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} while (dev->bus->self);
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*pinp = pin;
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/* The slot is the slot of the last bridge. */
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}
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return PCI_SLOT(dev->devfn);
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}
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/* This needs to be shunted out of here into the board specific bit */
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static int __init map_cayman_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int result = -1;
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/* The complication here is that the PCI IRQ lines from the Cayman's 2
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5V slots get into the CPU via a different path from the IRQ lines
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from the 3 3.3V slots. Thus, we have to detect whether the card's
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interrupts go via the 5V or 3.3V path, i.e. the 'bridge swizzling'
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at the point where we cross from 5V to 3.3V is not the normal case.
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The added complication is that we don't know that the 5V slots are
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always bus 2, because a card containing a PCI-PCI bridge may be
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plugged into a 3.3V slot, and this changes the bus numbering.
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Also, the Cayman has an intermediate PCI bus that goes a custom
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expansion board header (and to the secondary bridge). This bus has
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never been used in practice.
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The 1ary onboard PCI-PCI bridge is device 3 on bus 0
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The 2ary onboard PCI-PCI bridge is device 0 on the 2ary bus of the 1ary bridge.
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*/
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struct slot_pin {
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int slot;
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int pin;
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} path[4];
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int i=0;
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while (dev->bus->number > 0) {
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slot = path[i].slot = PCI_SLOT(dev->devfn);
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pin = path[i].pin = bridge_swizzle(pin, slot);
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dev = dev->bus->self;
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i++;
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if (i > 3) panic("PCI path to root bus too long!\n");
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}
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slot = PCI_SLOT(dev->devfn);
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/* This is the slot on bus 0 through which the device is eventually
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reachable. */
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/* Now work back up. */
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if ((slot < 3) || (i == 0)) {
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/* Bus 0 (incl. PCI-PCI bridge itself) : perform the final
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swizzle now. */
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result = IRQ_INTA + bridge_swizzle(pin, slot) - 1;
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} else {
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i--;
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slot = path[i].slot;
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pin = path[i].pin;
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if (slot > 0) {
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panic("PCI expansion bus device found - not handled!\n");
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} else {
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if (i > 0) {
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/* 5V slots */
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i--;
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slot = path[i].slot;
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pin = path[i].pin;
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/* 'pin' was swizzled earlier wrt slot, don't do it again. */
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result = IRQ_P2INTA + (pin - 1);
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} else {
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/* IRQ for 2ary PCI-PCI bridge : unused */
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result = -1;
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}
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}
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}
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return result;
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}
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irqreturn_t pcish5_err_irq(int irq, void *dev_id, struct pt_regs *regs)
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{
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unsigned pci_int, pci_air, pci_cir, pci_aint;
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pci_int = SH5PCI_READ(INT);
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pci_cir = SH5PCI_READ(CIR);
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pci_air = SH5PCI_READ(AIR);
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if (pci_int) {
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printk("PCI INTERRUPT (at %08llx)!\n", regs->pc);
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printk("PCI INT -> 0x%x\n", pci_int & 0xffff);
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printk("PCI AIR -> 0x%x\n", pci_air);
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printk("PCI CIR -> 0x%x\n", pci_cir);
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SH5PCI_WRITE(INT, ~0);
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}
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pci_aint = SH5PCI_READ(AINT);
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if (pci_aint) {
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printk("PCI ARB INTERRUPT!\n");
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printk("PCI AINT -> 0x%x\n", pci_aint);
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printk("PCI AIR -> 0x%x\n", pci_air);
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printk("PCI CIR -> 0x%x\n", pci_cir);
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SH5PCI_WRITE(AINT, ~0);
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}
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return IRQ_HANDLED;
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}
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irqreturn_t pcish5_serr_irq(int irq, void *dev_id, struct pt_regs *regs)
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{
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printk("SERR IRQ\n");
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return IRQ_NONE;
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}
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#define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1))
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static void __init
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pcibios_size_bridge(struct pci_bus *bus, struct resource *ior,
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struct resource *memr)
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{
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struct resource io_res, mem_res;
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struct pci_dev *dev;
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struct pci_dev *bridge = bus->self;
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struct list_head *ln;
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if (!bridge)
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return; /* host bridge, nothing to do */
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/* set reasonable default locations for pcibios_align_resource */
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io_res.start = PCIBIOS_MIN_IO;
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mem_res.start = PCIBIOS_MIN_MEM;
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io_res.end = io_res.start;
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mem_res.end = mem_res.start;
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/* Collect information about how our direct children are layed out. */
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for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
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int i;
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dev = pci_dev_b(ln);
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/* Skip bridges for now */
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if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI)
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continue;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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struct resource res;
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unsigned long size;
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memcpy(&res, &dev->resource[i], sizeof(res));
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size = res.end - res.start + 1;
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if (res.flags & IORESOURCE_IO) {
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res.start = io_res.end;
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pcibios_align_resource(dev, &res, size, 0);
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io_res.end = res.start + size;
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} else if (res.flags & IORESOURCE_MEM) {
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res.start = mem_res.end;
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pcibios_align_resource(dev, &res, size, 0);
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mem_res.end = res.start + size;
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}
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}
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}
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/* And for all of the subordinate busses. */
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for (ln=bus->children.next; ln != &bus->children; ln=ln->next)
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pcibios_size_bridge(pci_bus_b(ln), &io_res, &mem_res);
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/* turn the ending locations into sizes (subtract start) */
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io_res.end -= io_res.start;
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mem_res.end -= mem_res.start;
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/* Align the sizes up by bridge rules */
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io_res.end = ROUND_UP(io_res.end, 4*1024) - 1;
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mem_res.end = ROUND_UP(mem_res.end, 1*1024*1024) - 1;
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/* Adjust the bridge's allocation requirements */
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bridge->resource[0].end = bridge->resource[0].start + io_res.end;
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bridge->resource[1].end = bridge->resource[1].start + mem_res.end;
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bridge->resource[PCI_BRIDGE_RESOURCES].end =
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bridge->resource[PCI_BRIDGE_RESOURCES].start + io_res.end;
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bridge->resource[PCI_BRIDGE_RESOURCES+1].end =
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bridge->resource[PCI_BRIDGE_RESOURCES+1].start + mem_res.end;
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/* adjust parent's resource requirements */
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if (ior) {
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ior->end = ROUND_UP(ior->end, 4*1024);
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ior->end += io_res.end;
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}
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if (memr) {
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memr->end = ROUND_UP(memr->end, 1*1024*1024);
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memr->end += mem_res.end;
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}
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}
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#undef ROUND_UP
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static void __init pcibios_size_bridges(void)
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{
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struct resource io_res, mem_res;
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memset(&io_res, 0, sizeof(io_res));
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memset(&mem_res, 0, sizeof(mem_res));
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pcibios_size_bridge(pci_root_bus, &io_res, &mem_res);
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}
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static int __init pcibios_init(void)
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{
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if (request_irq(IRQ_ERR, pcish5_err_irq,
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SA_INTERRUPT, "PCI Error",NULL) < 0) {
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printk(KERN_ERR "PCISH5: Cannot hook PCI_PERR interrupt\n");
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return -EINVAL;
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}
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if (request_irq(IRQ_SERR, pcish5_serr_irq,
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SA_INTERRUPT, "PCI SERR interrupt", NULL) < 0) {
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printk(KERN_ERR "PCISH5: Cannot hook PCI_SERR interrupt\n");
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return -EINVAL;
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}
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|
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/* The pci subsytem needs to know where memory is and how much
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* of it there is. I've simply made these globals. A better mechanism
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* is probably needed.
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*/
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sh5pci_init(__pa(memory_start),
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__pa(memory_end) - __pa(memory_start));
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pci_root_bus = pci_scan_bus(0, &pci_config_ops, NULL);
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pcibios_size_bridges();
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pci_assign_unassigned_resources();
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|
pci_fixup_irqs(no_swizzle, map_cayman_irq);
|
|
|
|
return 0;
|
|
}
|
|
|
|
subsys_initcall(pcibios_init);
|
|
|
|
void __init pcibios_fixup_bus(struct pci_bus *bus)
|
|
{
|
|
struct pci_dev *dev = bus->self;
|
|
int i;
|
|
|
|
#if 1
|
|
if(dev) {
|
|
for(i=0; i<3; i++) {
|
|
bus->resource[i] =
|
|
&dev->resource[PCI_BRIDGE_RESOURCES+i];
|
|
bus->resource[i]->name = bus->name;
|
|
}
|
|
bus->resource[0]->flags |= IORESOURCE_IO;
|
|
bus->resource[1]->flags |= IORESOURCE_MEM;
|
|
|
|
/* For now, propagate host limits to the bus;
|
|
* we'll adjust them later. */
|
|
|
|
#if 1
|
|
bus->resource[0]->end = 64*1024 - 1 ;
|
|
bus->resource[1]->end = PCIBIOS_MIN_MEM+(256*1024*1024)-1;
|
|
bus->resource[0]->start = PCIBIOS_MIN_IO;
|
|
bus->resource[1]->start = PCIBIOS_MIN_MEM;
|
|
#else
|
|
bus->resource[0]->end = 0
|
|
bus->resource[1]->end = 0
|
|
bus->resource[0]->start =0
|
|
bus->resource[1]->start = 0;
|
|
#endif
|
|
/* Turn off downstream PF memory address range by default */
|
|
bus->resource[2]->start = 1024*1024;
|
|
bus->resource[2]->end = bus->resource[2]->start - 1;
|
|
}
|
|
#endif
|
|
|
|
}
|
|
|