825fd08dbb
Test for definedness of the macro which is actually defined, and which matches the name of the file. Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk> Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
181 lines
5.5 KiB
C
181 lines
5.5 KiB
C
/*
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* ADV7343 encoder related structure and register definitions
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*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed .as is. WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef ADV7343_REGS_H
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#define ADV7343_REGS_H
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struct adv7343_std_info {
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u32 standard_val3;
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u32 fsc_val;
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v4l2_std_id stdid;
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};
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/* Register offset macros */
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#define ADV7343_POWER_MODE_REG (0x00)
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#define ADV7343_MODE_SELECT_REG (0x01)
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#define ADV7343_MODE_REG0 (0x02)
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#define ADV7343_DAC2_OUTPUT_LEVEL (0x0b)
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#define ADV7343_SOFT_RESET (0x17)
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#define ADV7343_HD_MODE_REG1 (0x30)
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#define ADV7343_HD_MODE_REG2 (0x31)
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#define ADV7343_HD_MODE_REG3 (0x32)
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#define ADV7343_HD_MODE_REG4 (0x33)
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#define ADV7343_HD_MODE_REG5 (0x34)
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#define ADV7343_HD_MODE_REG6 (0x35)
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#define ADV7343_HD_MODE_REG7 (0x39)
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#define ADV7343_SD_MODE_REG1 (0x80)
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#define ADV7343_SD_MODE_REG2 (0x82)
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#define ADV7343_SD_MODE_REG3 (0x83)
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#define ADV7343_SD_MODE_REG4 (0x84)
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#define ADV7343_SD_MODE_REG5 (0x86)
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#define ADV7343_SD_MODE_REG6 (0x87)
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#define ADV7343_SD_MODE_REG7 (0x88)
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#define ADV7343_SD_MODE_REG8 (0x89)
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#define ADV7343_FSC_REG0 (0x8C)
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#define ADV7343_FSC_REG1 (0x8D)
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#define ADV7343_FSC_REG2 (0x8E)
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#define ADV7343_FSC_REG3 (0x8F)
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#define ADV7343_SD_CGMS_WSS0 (0x99)
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#define ADV7343_SD_HUE_REG (0xA0)
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#define ADV7343_SD_BRIGHTNESS_WSS (0xA1)
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/* Default values for the registers */
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#define ADV7343_POWER_MODE_REG_DEFAULT (0x10)
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#define ADV7343_HD_MODE_REG1_DEFAULT (0x3C) /* Changed Default
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720p EAVSAV code*/
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#define ADV7343_HD_MODE_REG2_DEFAULT (0x01) /* Changed Pixel data
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valid */
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#define ADV7343_HD_MODE_REG3_DEFAULT (0x00) /* Color delay 0 clks */
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#define ADV7343_HD_MODE_REG4_DEFAULT (0xE8) /* Changed */
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#define ADV7343_HD_MODE_REG5_DEFAULT (0x08)
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#define ADV7343_HD_MODE_REG6_DEFAULT (0x00)
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#define ADV7343_HD_MODE_REG7_DEFAULT (0x00)
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#define ADV7343_SD_MODE_REG8_DEFAULT (0x00)
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#define ADV7343_SOFT_RESET_DEFAULT (0x02)
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#define ADV7343_COMPOSITE_POWER_VALUE (0x80)
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#define ADV7343_COMPONENT_POWER_VALUE (0x1C)
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#define ADV7343_SVIDEO_POWER_VALUE (0x60)
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#define ADV7343_SD_HUE_REG_DEFAULT (127)
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#define ADV7343_SD_BRIGHTNESS_WSS_DEFAULT (0x03)
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#define ADV7343_SD_CGMS_WSS0_DEFAULT (0x10)
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#define ADV7343_SD_MODE_REG1_DEFAULT (0x00)
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#define ADV7343_SD_MODE_REG2_DEFAULT (0xC9)
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#define ADV7343_SD_MODE_REG3_DEFAULT (0x10)
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#define ADV7343_SD_MODE_REG4_DEFAULT (0x01)
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#define ADV7343_SD_MODE_REG5_DEFAULT (0x02)
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#define ADV7343_SD_MODE_REG6_DEFAULT (0x0C)
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#define ADV7343_SD_MODE_REG7_DEFAULT (0x04)
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#define ADV7343_SD_MODE_REG8_DEFAULT (0x00)
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/* Bit masks for Mode Select Register */
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#define INPUT_MODE_MASK (0x70)
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#define SD_INPUT_MODE (0x00)
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#define HD_720P_INPUT_MODE (0x10)
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#define HD_1080I_INPUT_MODE (0x10)
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/* Bit masks for Mode Register 0 */
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#define TEST_PATTERN_BLACK_BAR_EN (0x04)
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#define YUV_OUTPUT_SELECT (0x20)
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#define RGB_OUTPUT_SELECT (0xDF)
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/* Bit masks for DAC output levels */
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#define DAC_OUTPUT_LEVEL_MASK (0xFF)
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/* Bit masks for soft reset register */
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#define SOFT_RESET (0x02)
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/* Bit masks for HD Mode Register 1 */
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#define OUTPUT_STD_MASK (0x03)
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#define OUTPUT_STD_SHIFT (0)
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#define OUTPUT_STD_EIA0_2 (0x00)
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#define OUTPUT_STD_EIA0_1 (0x01)
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#define OUTPUT_STD_FULL (0x02)
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#define EMBEDDED_SYNC (0x04)
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#define EXTERNAL_SYNC (0xFB)
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#define STD_MODE_SHIFT (3)
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#define STD_MODE_MASK (0x1F)
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#define STD_MODE_720P (0x05)
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#define STD_MODE_720P_25 (0x08)
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#define STD_MODE_720P_30 (0x07)
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#define STD_MODE_720P_50 (0x06)
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#define STD_MODE_1080I (0x0D)
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#define STD_MODE_1080I_25fps (0x0E)
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#define STD_MODE_1080P_24 (0x12)
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#define STD_MODE_1080P_25 (0x10)
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#define STD_MODE_1080P_30 (0x0F)
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#define STD_MODE_525P (0x00)
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#define STD_MODE_625P (0x03)
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/* Bit masks for SD Mode Register 1 */
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#define SD_STD_MASK (0x03)
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#define SD_STD_NTSC (0x00)
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#define SD_STD_PAL_BDGHI (0x01)
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#define SD_STD_PAL_M (0x02)
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#define SD_STD_PAL_N (0x03)
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#define SD_LUMA_FLTR_MASK (0x7)
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#define SD_LUMA_FLTR_SHIFT (0x2)
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#define SD_CHROMA_FLTR_MASK (0x7)
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#define SD_CHROMA_FLTR_SHIFT (0x5)
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/* Bit masks for SD Mode Register 2 */
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#define SD_PBPR_SSAF_EN (0x01)
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#define SD_PBPR_SSAF_DI (0xFE)
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#define SD_DAC_1_DI (0xFD)
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#define SD_DAC_2_DI (0xFB)
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#define SD_PEDESTAL_EN (0x08)
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#define SD_PEDESTAL_DI (0xF7)
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#define SD_SQUARE_PIXEL_EN (0x10)
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#define SD_SQUARE_PIXEL_DI (0xEF)
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#define SD_PIXEL_DATA_VALID (0x40)
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#define SD_ACTIVE_EDGE_EN (0x80)
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#define SD_ACTIVE_EDGE_DI (0x7F)
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/* Bit masks for HD Mode Register 6 */
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#define HD_RGB_INPUT_EN (0x02)
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#define HD_RGB_INPUT_DI (0xFD)
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#define HD_PBPR_SYNC_EN (0x04)
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#define HD_PBPR_SYNC_DI (0xFB)
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#define HD_DAC_SWAP_EN (0x08)
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#define HD_DAC_SWAP_DI (0xF7)
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#define HD_GAMMA_CURVE_A (0xEF)
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#define HD_GAMMA_CURVE_B (0x10)
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#define HD_GAMMA_EN (0x20)
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#define HD_GAMMA_DI (0xDF)
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#define HD_ADPT_FLTR_MODEB (0x40)
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#define HD_ADPT_FLTR_MODEA (0xBF)
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#define HD_ADPT_FLTR_EN (0x80)
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#define HD_ADPT_FLTR_DI (0x7F)
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#define ADV7343_BRIGHTNESS_MAX (127)
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#define ADV7343_BRIGHTNESS_MIN (0)
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#define ADV7343_BRIGHTNESS_DEF (3)
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#define ADV7343_HUE_MAX (255)
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#define ADV7343_HUE_MIN (0)
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#define ADV7343_HUE_DEF (127)
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#define ADV7343_GAIN_MAX (64)
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#define ADV7343_GAIN_MIN (-64)
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#define ADV7343_GAIN_DEF (0)
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#endif
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