645 lines
17 KiB
C
645 lines
17 KiB
C
/* This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
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because MTRRs can span upto 40 bits (36bits on most modern x86) */
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <asm/io.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include <asm/system.h>
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#include <asm/cpufeature.h>
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#include <asm/processor-flags.h>
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#include <asm/tlbflush.h>
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#include <asm/pat.h>
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#include "mtrr.h"
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struct mtrr_state {
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struct mtrr_var_range var_ranges[MAX_VAR_RANGES];
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mtrr_type fixed_ranges[NUM_FIXED_RANGES];
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unsigned char enabled;
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unsigned char have_fixed;
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mtrr_type def_type;
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};
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struct fixed_range_block {
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int base_msr; /* start address of an MTRR block */
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int ranges; /* number of MTRRs in this block */
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};
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static struct fixed_range_block fixed_range_blocks[] = {
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{ MTRRfix64K_00000_MSR, 1 }, /* one 64k MTRR */
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{ MTRRfix16K_80000_MSR, 2 }, /* two 16k MTRRs */
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{ MTRRfix4K_C0000_MSR, 8 }, /* eight 4k MTRRs */
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{}
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};
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static unsigned long smp_changes_mask;
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static struct mtrr_state mtrr_state = {};
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static int mtrr_state_set;
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static u64 tom2;
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#undef MODULE_PARAM_PREFIX
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#define MODULE_PARAM_PREFIX "mtrr."
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static int mtrr_show;
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module_param_named(show, mtrr_show, bool, 0);
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/*
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* Returns the effective MTRR type for the region
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* Error returns:
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* - 0xFE - when the range is "not entirely covered" by _any_ var range MTRR
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* - 0xFF - when MTRR is not enabled
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*/
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u8 mtrr_type_lookup(u64 start, u64 end)
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{
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int i;
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u64 base, mask;
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u8 prev_match, curr_match;
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if (!mtrr_state_set)
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return 0xFF;
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if (!mtrr_state.enabled)
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return 0xFF;
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/* Make end inclusive end, instead of exclusive */
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end--;
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/* Look in fixed ranges. Just return the type as per start */
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if (mtrr_state.have_fixed && (start < 0x100000)) {
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int idx;
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if (start < 0x80000) {
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idx = 0;
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idx += (start >> 16);
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return mtrr_state.fixed_ranges[idx];
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} else if (start < 0xC0000) {
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idx = 1 * 8;
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idx += ((start - 0x80000) >> 14);
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return mtrr_state.fixed_ranges[idx];
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} else if (start < 0x1000000) {
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idx = 3 * 8;
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idx += ((start - 0xC0000) >> 12);
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return mtrr_state.fixed_ranges[idx];
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}
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}
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/*
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* Look in variable ranges
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* Look of multiple ranges matching this address and pick type
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* as per MTRR precedence
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*/
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if (!mtrr_state.enabled & 2) {
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return mtrr_state.def_type;
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}
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prev_match = 0xFF;
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for (i = 0; i < num_var_ranges; ++i) {
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unsigned short start_state, end_state;
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if (!(mtrr_state.var_ranges[i].mask_lo & (1 << 11)))
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continue;
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base = (((u64)mtrr_state.var_ranges[i].base_hi) << 32) +
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(mtrr_state.var_ranges[i].base_lo & PAGE_MASK);
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mask = (((u64)mtrr_state.var_ranges[i].mask_hi) << 32) +
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(mtrr_state.var_ranges[i].mask_lo & PAGE_MASK);
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start_state = ((start & mask) == (base & mask));
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end_state = ((end & mask) == (base & mask));
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if (start_state != end_state)
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return 0xFE;
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if ((start & mask) != (base & mask)) {
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continue;
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}
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curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;
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if (prev_match == 0xFF) {
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prev_match = curr_match;
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continue;
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}
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if (prev_match == MTRR_TYPE_UNCACHABLE ||
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curr_match == MTRR_TYPE_UNCACHABLE) {
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return MTRR_TYPE_UNCACHABLE;
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}
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if ((prev_match == MTRR_TYPE_WRBACK &&
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curr_match == MTRR_TYPE_WRTHROUGH) ||
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(prev_match == MTRR_TYPE_WRTHROUGH &&
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curr_match == MTRR_TYPE_WRBACK)) {
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prev_match = MTRR_TYPE_WRTHROUGH;
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curr_match = MTRR_TYPE_WRTHROUGH;
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}
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if (prev_match != curr_match) {
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return MTRR_TYPE_UNCACHABLE;
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}
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}
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if (tom2) {
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if (start >= (1ULL<<32) && (end < tom2))
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return MTRR_TYPE_WRBACK;
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}
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if (prev_match != 0xFF)
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return prev_match;
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return mtrr_state.def_type;
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}
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/* Get the MSR pair relating to a var range */
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static void
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get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
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{
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rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
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rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
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}
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static void
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get_fixed_ranges(mtrr_type * frs)
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{
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unsigned int *p = (unsigned int *) frs;
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int i;
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rdmsr(MTRRfix64K_00000_MSR, p[0], p[1]);
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for (i = 0; i < 2; i++)
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rdmsr(MTRRfix16K_80000_MSR + i, p[2 + i * 2], p[3 + i * 2]);
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for (i = 0; i < 8; i++)
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rdmsr(MTRRfix4K_C0000_MSR + i, p[6 + i * 2], p[7 + i * 2]);
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}
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void mtrr_save_fixed_ranges(void *info)
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{
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if (cpu_has_mtrr)
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get_fixed_ranges(mtrr_state.fixed_ranges);
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}
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static void print_fixed(unsigned base, unsigned step, const mtrr_type*types)
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{
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unsigned i;
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for (i = 0; i < 8; ++i, ++types, base += step)
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printk(KERN_INFO "MTRR %05X-%05X %s\n",
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base, base + step - 1, mtrr_attrib_to_str(*types));
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}
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static void prepare_set(void);
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static void post_set(void);
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/* Grab all of the MTRR state for this CPU into *state */
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void __init get_mtrr_state(void)
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{
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unsigned int i;
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struct mtrr_var_range *vrs;
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unsigned lo, dummy;
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unsigned long flags;
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vrs = mtrr_state.var_ranges;
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rdmsr(MTRRcap_MSR, lo, dummy);
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mtrr_state.have_fixed = (lo >> 8) & 1;
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for (i = 0; i < num_var_ranges; i++)
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get_mtrr_var_range(i, &vrs[i]);
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if (mtrr_state.have_fixed)
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get_fixed_ranges(mtrr_state.fixed_ranges);
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rdmsr(MTRRdefType_MSR, lo, dummy);
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mtrr_state.def_type = (lo & 0xff);
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mtrr_state.enabled = (lo & 0xc00) >> 10;
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if (amd_special_default_mtrr()) {
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unsigned lo, hi;
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/* TOP_MEM2 */
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rdmsr(MSR_K8_TOP_MEM2, lo, hi);
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tom2 = hi;
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tom2 <<= 32;
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tom2 |= lo;
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tom2 &= 0xffffff8000000ULL;
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}
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if (mtrr_show) {
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int high_width;
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printk(KERN_INFO "MTRR default type: %s\n", mtrr_attrib_to_str(mtrr_state.def_type));
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if (mtrr_state.have_fixed) {
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printk(KERN_INFO "MTRR fixed ranges %sabled:\n",
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mtrr_state.enabled & 1 ? "en" : "dis");
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print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);
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for (i = 0; i < 2; ++i)
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print_fixed(0x80000 + i * 0x20000, 0x04000, mtrr_state.fixed_ranges + (i + 1) * 8);
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for (i = 0; i < 8; ++i)
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print_fixed(0xC0000 + i * 0x08000, 0x01000, mtrr_state.fixed_ranges + (i + 3) * 8);
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}
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printk(KERN_INFO "MTRR variable ranges %sabled:\n",
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mtrr_state.enabled & 2 ? "en" : "dis");
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high_width = ((size_or_mask ? ffs(size_or_mask) - 1 : 32) - (32 - PAGE_SHIFT) + 3) / 4;
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for (i = 0; i < num_var_ranges; ++i) {
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if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
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printk(KERN_INFO "MTRR %u base %0*X%05X000 mask %0*X%05X000 %s\n",
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i,
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high_width,
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mtrr_state.var_ranges[i].base_hi,
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mtrr_state.var_ranges[i].base_lo >> 12,
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high_width,
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mtrr_state.var_ranges[i].mask_hi,
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mtrr_state.var_ranges[i].mask_lo >> 12,
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mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));
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else
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printk(KERN_INFO "MTRR %u disabled\n", i);
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}
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if (tom2) {
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printk(KERN_INFO "TOM2: %016llx aka %lldM\n",
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tom2, tom2>>20);
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}
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}
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mtrr_state_set = 1;
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/* PAT setup for BP. We need to go through sync steps here */
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local_irq_save(flags);
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prepare_set();
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pat_init();
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post_set();
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local_irq_restore(flags);
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}
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/* Some BIOS's are fucked and don't set all MTRRs the same! */
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void __init mtrr_state_warn(void)
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{
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unsigned long mask = smp_changes_mask;
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if (!mask)
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return;
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if (mask & MTRR_CHANGE_MASK_FIXED)
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printk(KERN_WARNING "mtrr: your CPUs had inconsistent fixed MTRR settings\n");
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if (mask & MTRR_CHANGE_MASK_VARIABLE)
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printk(KERN_WARNING "mtrr: your CPUs had inconsistent variable MTRR settings\n");
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if (mask & MTRR_CHANGE_MASK_DEFTYPE)
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printk(KERN_WARNING "mtrr: your CPUs had inconsistent MTRRdefType settings\n");
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printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
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printk(KERN_INFO "mtrr: corrected configuration.\n");
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}
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/* Doesn't attempt to pass an error out to MTRR users
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because it's quite complicated in some cases and probably not
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worth it because the best error handling is to ignore it. */
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void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
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{
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if (wrmsr_safe(msr, a, b) < 0)
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printk(KERN_ERR
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"MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
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smp_processor_id(), msr, a, b);
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}
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/**
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* Enable and allow read/write of extended fixed-range MTRR bits on K8 CPUs
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* see AMD publication no. 24593, chapter 3.2.1 for more information
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*/
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static inline void k8_enable_fixed_iorrs(void)
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{
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unsigned lo, hi;
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rdmsr(MSR_K8_SYSCFG, lo, hi);
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mtrr_wrmsr(MSR_K8_SYSCFG, lo
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| K8_MTRRFIXRANGE_DRAM_ENABLE
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| K8_MTRRFIXRANGE_DRAM_MODIFY, hi);
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}
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/**
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* set_fixed_range - checks & updates a fixed-range MTRR if it differs from the value it should have
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* @msr: MSR address of the MTTR which should be checked and updated
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* @changed: pointer which indicates whether the MTRR needed to be changed
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* @msrwords: pointer to the MSR values which the MSR should have
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*
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* If K8 extentions are wanted, update the K8 SYSCFG MSR also.
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* See AMD publication no. 24593, chapter 7.8.1, page 233 for more information.
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*/
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static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
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{
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unsigned lo, hi;
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rdmsr(msr, lo, hi);
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if (lo != msrwords[0] || hi != msrwords[1]) {
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
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boot_cpu_data.x86 == 15 &&
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((msrwords[0] | msrwords[1]) & K8_MTRR_RDMEM_WRMEM_MASK))
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k8_enable_fixed_iorrs();
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mtrr_wrmsr(msr, msrwords[0], msrwords[1]);
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*changed = true;
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}
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}
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/**
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* generic_get_free_region - Get a free MTRR.
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* @base: The starting (base) address of the region.
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* @size: The size (in bytes) of the region.
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* @replace_reg: mtrr index to be replaced; set to invalid value if none.
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*
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* Returns: The index of the region on success, else negative on error.
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*/
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int generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
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{
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int i, max;
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mtrr_type ltype;
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unsigned long lbase, lsize;
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max = num_var_ranges;
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if (replace_reg >= 0 && replace_reg < max)
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return replace_reg;
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for (i = 0; i < max; ++i) {
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mtrr_if->get(i, &lbase, &lsize, <ype);
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if (lsize == 0)
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return i;
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}
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return -ENOSPC;
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}
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static void generic_get_mtrr(unsigned int reg, unsigned long *base,
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unsigned long *size, mtrr_type *type)
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{
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unsigned int mask_lo, mask_hi, base_lo, base_hi;
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rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
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if ((mask_lo & 0x800) == 0) {
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/* Invalid (i.e. free) range */
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*base = 0;
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*size = 0;
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*type = 0;
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return;
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}
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rdmsr(MTRRphysBase_MSR(reg), base_lo, base_hi);
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/* Work out the shifted address mask. */
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mask_lo = size_or_mask | mask_hi << (32 - PAGE_SHIFT)
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| mask_lo >> PAGE_SHIFT;
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/* This works correctly if size is a power of two, i.e. a
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contiguous range. */
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*size = -mask_lo;
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*base = base_hi << (32 - PAGE_SHIFT) | base_lo >> PAGE_SHIFT;
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*type = base_lo & 0xff;
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}
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/**
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* set_fixed_ranges - checks & updates the fixed-range MTRRs if they differ from the saved set
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* @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
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*/
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static int set_fixed_ranges(mtrr_type * frs)
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{
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unsigned long long *saved = (unsigned long long *) frs;
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bool changed = false;
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int block=-1, range;
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while (fixed_range_blocks[++block].ranges)
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for (range=0; range < fixed_range_blocks[block].ranges; range++)
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set_fixed_range(fixed_range_blocks[block].base_msr + range,
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&changed, (unsigned int *) saved++);
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return changed;
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}
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/* Set the MSR pair relating to a var range. Returns TRUE if
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changes are made */
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static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
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{
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unsigned int lo, hi;
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bool changed = false;
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rdmsr(MTRRphysBase_MSR(index), lo, hi);
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if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
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|| (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
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(hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
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mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
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changed = true;
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}
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rdmsr(MTRRphysMask_MSR(index), lo, hi);
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if ((vr->mask_lo & 0xfffff800UL) != (lo & 0xfffff800UL)
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|| (vr->mask_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
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(hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
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mtrr_wrmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
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changed = true;
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}
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return changed;
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}
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static u32 deftype_lo, deftype_hi;
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/**
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* set_mtrr_state - Set the MTRR state for this CPU.
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*
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* NOTE: The CPU must already be in a safe state for MTRR changes.
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* RETURNS: 0 if no changes made, else a mask indicating what was changed.
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*/
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static unsigned long set_mtrr_state(void)
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{
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unsigned int i;
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unsigned long change_mask = 0;
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for (i = 0; i < num_var_ranges; i++)
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if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
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change_mask |= MTRR_CHANGE_MASK_VARIABLE;
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if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
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change_mask |= MTRR_CHANGE_MASK_FIXED;
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/* Set_mtrr_restore restores the old value of MTRRdefType,
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so to set it we fiddle with the saved value */
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if ((deftype_lo & 0xff) != mtrr_state.def_type
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|| ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
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deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type | (mtrr_state.enabled << 10);
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change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
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}
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return change_mask;
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}
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static unsigned long cr4 = 0;
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static DEFINE_SPINLOCK(set_atomicity_lock);
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|
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/*
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* Since we are disabling the cache don't allow any interrupts - they
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* would run extremely slow and would only increase the pain. The caller must
|
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* ensure that local interrupts are disabled and are reenabled after post_set()
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* has been called.
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*/
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static void prepare_set(void) __acquires(set_atomicity_lock)
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{
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unsigned long cr0;
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|
|
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/* Note that this is not ideal, since the cache is only flushed/disabled
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for this CPU while the MTRRs are changed, but changing this requires
|
|
more invasive changes to the way the kernel boots */
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|
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spin_lock(&set_atomicity_lock);
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|
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/* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
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cr0 = read_cr0() | X86_CR0_CD;
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write_cr0(cr0);
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wbinvd();
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|
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/* Save value of CR4 and clear Page Global Enable (bit 7) */
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if ( cpu_has_pge ) {
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cr4 = read_cr4();
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write_cr4(cr4 & ~X86_CR4_PGE);
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|
}
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|
|
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/* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
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|
__flush_tlb();
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|
|
|
/* Save MTRR state */
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|
rdmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);
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|
|
|
/* Disable MTRRs, and set the default type to uncached */
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|
mtrr_wrmsr(MTRRdefType_MSR, deftype_lo & ~0xcff, deftype_hi);
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}
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|
|
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static void post_set(void) __releases(set_atomicity_lock)
|
|
{
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|
/* Flush TLBs (no need to flush caches - they are disabled) */
|
|
__flush_tlb();
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|
|
|
/* Intel (P6) standard MTRRs */
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|
mtrr_wrmsr(MTRRdefType_MSR, deftype_lo, deftype_hi);
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|
|
|
/* Enable caches */
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|
write_cr0(read_cr0() & 0xbfffffff);
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|
|
|
/* Restore value of CR4 */
|
|
if ( cpu_has_pge )
|
|
write_cr4(cr4);
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|
spin_unlock(&set_atomicity_lock);
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|
}
|
|
|
|
static void generic_set_all(void)
|
|
{
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|
unsigned long mask, count;
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
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|
prepare_set();
|
|
|
|
/* Actually set the state */
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|
mask = set_mtrr_state();
|
|
|
|
/* also set PAT */
|
|
pat_init();
|
|
|
|
post_set();
|
|
local_irq_restore(flags);
|
|
|
|
/* Use the atomic bitops to update the global mask */
|
|
for (count = 0; count < sizeof mask * 8; ++count) {
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|
if (mask & 0x01)
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|
set_bit(count, &smp_changes_mask);
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|
mask >>= 1;
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|
}
|
|
|
|
}
|
|
|
|
static void generic_set_mtrr(unsigned int reg, unsigned long base,
|
|
unsigned long size, mtrr_type type)
|
|
/* [SUMMARY] Set variable MTRR register on the local CPU.
|
|
<reg> The register to set.
|
|
<base> The base address of the region.
|
|
<size> The size of the region. If this is 0 the region is disabled.
|
|
<type> The type of the region.
|
|
[RETURNS] Nothing.
|
|
*/
|
|
{
|
|
unsigned long flags;
|
|
struct mtrr_var_range *vr;
|
|
|
|
vr = &mtrr_state.var_ranges[reg];
|
|
|
|
local_irq_save(flags);
|
|
prepare_set();
|
|
|
|
if (size == 0) {
|
|
/* The invalid bit is kept in the mask, so we simply clear the
|
|
relevant mask register to disable a range. */
|
|
mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
|
|
memset(vr, 0, sizeof(struct mtrr_var_range));
|
|
} else {
|
|
vr->base_lo = base << PAGE_SHIFT | type;
|
|
vr->base_hi = (base & size_and_mask) >> (32 - PAGE_SHIFT);
|
|
vr->mask_lo = -size << PAGE_SHIFT | 0x800;
|
|
vr->mask_hi = (-size & size_and_mask) >> (32 - PAGE_SHIFT);
|
|
|
|
mtrr_wrmsr(MTRRphysBase_MSR(reg), vr->base_lo, vr->base_hi);
|
|
mtrr_wrmsr(MTRRphysMask_MSR(reg), vr->mask_lo, vr->mask_hi);
|
|
}
|
|
|
|
post_set();
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
int generic_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
|
|
{
|
|
unsigned long lbase, last;
|
|
|
|
/* For Intel PPro stepping <= 7, must be 4 MiB aligned
|
|
and not touch 0x70000000->0x7003FFFF */
|
|
if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
|
|
boot_cpu_data.x86_model == 1 &&
|
|
boot_cpu_data.x86_mask <= 7) {
|
|
if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
|
|
printk(KERN_WARNING "mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
|
|
return -EINVAL;
|
|
}
|
|
if (!(base + size < 0x70000 || base > 0x7003F) &&
|
|
(type == MTRR_TYPE_WRCOMB
|
|
|| type == MTRR_TYPE_WRBACK)) {
|
|
printk(KERN_WARNING "mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
/* Check upper bits of base and last are equal and lower bits are 0
|
|
for base and 1 for last */
|
|
last = base + size - 1;
|
|
for (lbase = base; !(lbase & 1) && (last & 1);
|
|
lbase = lbase >> 1, last = last >> 1) ;
|
|
if (lbase != last) {
|
|
printk(KERN_WARNING "mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n",
|
|
base, size);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
static int generic_have_wrcomb(void)
|
|
{
|
|
unsigned long config, dummy;
|
|
rdmsr(MTRRcap_MSR, config, dummy);
|
|
return (config & (1 << 10));
|
|
}
|
|
|
|
int positive_have_wrcomb(void)
|
|
{
|
|
return 1;
|
|
}
|
|
|
|
/* generic structure...
|
|
*/
|
|
struct mtrr_ops generic_mtrr_ops = {
|
|
.use_intel_if = 1,
|
|
.set_all = generic_set_all,
|
|
.get = generic_get_mtrr,
|
|
.get_free_region = generic_get_free_region,
|
|
.set = generic_set_mtrr,
|
|
.validate_add_page = generic_validate_add_page,
|
|
.have_wrcomb = generic_have_wrcomb,
|
|
};
|