df9ee29270
Fix the IRQ flag handling naming. In linux/irqflags.h under one configuration, it maps: local_irq_enable() -> raw_local_irq_enable() local_irq_disable() -> raw_local_irq_disable() local_irq_save() -> raw_local_irq_save() ... and under the other configuration, it maps: raw_local_irq_enable() -> local_irq_enable() raw_local_irq_disable() -> local_irq_disable() raw_local_irq_save() -> local_irq_save() ... This is quite confusing. There should be one set of names expected of the arch, and this should be wrapped to give another set of names that are expected by users of this facility. Change this to have the arch provide: flags = arch_local_save_flags() flags = arch_local_irq_save() arch_local_irq_restore(flags) arch_local_irq_disable() arch_local_irq_enable() arch_irqs_disabled_flags(flags) arch_irqs_disabled() arch_safe_halt() Then linux/irqflags.h wraps these to provide: raw_local_save_flags(flags) raw_local_irq_save(flags) raw_local_irq_restore(flags) raw_local_irq_disable() raw_local_irq_enable() raw_irqs_disabled_flags(flags) raw_irqs_disabled() raw_safe_halt() with type checking on the flags 'arguments', and then wraps those to provide: local_save_flags(flags) local_irq_save(flags) local_irq_restore(flags) local_irq_disable() local_irq_enable() irqs_disabled_flags(flags) irqs_disabled() safe_halt() with tracing included if enabled. The arch functions can now all be inline functions rather than some of them having to be macros. Signed-off-by: David Howells <dhowells@redhat.com> [X86, FRV, MN10300] Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> [Tile] Signed-off-by: Michal Simek <monstr@monstr.eu> [Microblaze] Tested-by: Catalin Marinas <catalin.marinas@arm.com> [ARM] Acked-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> [AVR] Acked-by: Tony Luck <tony.luck@intel.com> [IA-64] Acked-by: Hirokazu Takata <takata@linux-m32r.org> [M32R] Acked-by: Greg Ungerer <gerg@uclinux.org> [M68K/M68KNOMMU] Acked-by: Ralf Baechle <ralf@linux-mips.org> [MIPS] Acked-by: Kyle McMartin <kyle@mcmartin.ca> [PA-RISC] Acked-by: Paul Mackerras <paulus@samba.org> [PowerPC] Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> [S390] Acked-by: Chen Liqin <liqin.chen@sunplusct.com> [Score] Acked-by: Matt Fleming <matt@console-pimps.org> [SH] Acked-by: David S. Miller <davem@davemloft.net> [Sparc] Acked-by: Chris Zankel <chris@zankel.net> [Xtensa] Reviewed-by: Richard Henderson <rth@twiddle.net> [Alpha] Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> [H8300] Cc: starvik@axis.com [CRIS] Cc: jesper.nilsson@axis.com [CRIS] Cc: linux-cris-kernel@axis.com
288 lines
6.6 KiB
C
288 lines
6.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
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* Copyright (C) 1996 by Paul M. Antoine
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* Copyright (C) 1999 Silicon Graphics
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*/
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#ifndef _ASM_IRQFLAGS_H
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#define _ASM_IRQFLAGS_H
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#ifndef __ASSEMBLY__
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#include <linux/compiler.h>
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#include <asm/hazards.h>
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__asm__(
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" .macro arch_local_irq_enable \n"
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" .set push \n"
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" .set reorder \n"
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" .set noat \n"
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#ifdef CONFIG_MIPS_MT_SMTC
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" mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n"
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" ori $1, 0x400 \n"
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" xori $1, 0x400 \n"
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" mtc0 $1, $2, 1 \n"
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#elif defined(CONFIG_CPU_MIPSR2)
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" ei \n"
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#else
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" mfc0 $1,$12 \n"
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" ori $1,0x1f \n"
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" xori $1,0x1e \n"
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" mtc0 $1,$12 \n"
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#endif
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" irq_enable_hazard \n"
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" .set pop \n"
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" .endm");
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extern void smtc_ipi_replay(void);
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static inline void arch_local_irq_enable(void)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* SMTC kernel needs to do a software replay of queued
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* IPIs, at the cost of call overhead on each local_irq_enable()
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*/
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smtc_ipi_replay();
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#endif
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__asm__ __volatile__(
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"arch_local_irq_enable"
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: /* no outputs */
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: /* no inputs */
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: "memory");
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}
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/*
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* For cli() we have to insert nops to make sure that the new value
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* has actually arrived in the status register before the end of this
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* macro.
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* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
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* no nops at all.
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*/
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/*
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* For TX49, operating only IE bit is not enough.
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*
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* If mfc0 $12 follows store and the mfc0 is last instruction of a
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* page and fetching the next instruction causes TLB miss, the result
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* of the mfc0 might wrongly contain EXL bit.
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*
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* ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
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*
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* Workaround: mask EXL bit of the result or place a nop before mfc0.
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*/
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__asm__(
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" .macro arch_local_irq_disable\n"
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" .set push \n"
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" .set noat \n"
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#ifdef CONFIG_MIPS_MT_SMTC
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" mfc0 $1, $2, 1 \n"
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" ori $1, 0x400 \n"
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" .set noreorder \n"
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" mtc0 $1, $2, 1 \n"
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#elif defined(CONFIG_CPU_MIPSR2)
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" di \n"
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#else
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" mfc0 $1,$12 \n"
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" ori $1,0x1f \n"
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" xori $1,0x1f \n"
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" .set noreorder \n"
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" mtc0 $1,$12 \n"
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#endif
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" irq_disable_hazard \n"
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" .set pop \n"
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" .endm \n");
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static inline void arch_local_irq_disable(void)
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{
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__asm__ __volatile__(
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"arch_local_irq_disable"
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: /* no outputs */
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: /* no inputs */
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: "memory");
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}
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__asm__(
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" .macro arch_local_save_flags flags \n"
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" .set push \n"
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" .set reorder \n"
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#ifdef CONFIG_MIPS_MT_SMTC
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" mfc0 \\flags, $2, 1 \n"
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#else
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" mfc0 \\flags, $12 \n"
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#endif
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" .set pop \n"
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" .endm \n");
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static inline unsigned long arch_local_save_flags(void)
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{
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unsigned long flags;
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asm volatile("arch_local_save_flags %0" : "=r" (flags));
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return flags;
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}
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__asm__(
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" .macro arch_local_irq_save result \n"
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" .set push \n"
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" .set reorder \n"
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" .set noat \n"
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#ifdef CONFIG_MIPS_MT_SMTC
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" mfc0 \\result, $2, 1 \n"
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" ori $1, \\result, 0x400 \n"
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" .set noreorder \n"
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" mtc0 $1, $2, 1 \n"
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" andi \\result, \\result, 0x400 \n"
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#elif defined(CONFIG_CPU_MIPSR2)
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" di \\result \n"
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" andi \\result, 1 \n"
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#else
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" mfc0 \\result, $12 \n"
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" ori $1, \\result, 0x1f \n"
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" xori $1, 0x1f \n"
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" .set noreorder \n"
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" mtc0 $1, $12 \n"
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#endif
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" irq_disable_hazard \n"
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" .set pop \n"
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" .endm \n");
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static inline unsigned long arch_local_irq_save(void)
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{
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unsigned long flags;
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asm volatile("arch_local_irq_save\t%0"
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: "=r" (flags)
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: /* no inputs */
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: "memory");
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return flags;
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}
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__asm__(
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" .macro arch_local_irq_restore flags \n"
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" .set push \n"
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" .set noreorder \n"
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" .set noat \n"
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#ifdef CONFIG_MIPS_MT_SMTC
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"mfc0 $1, $2, 1 \n"
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"andi \\flags, 0x400 \n"
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"ori $1, 0x400 \n"
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"xori $1, 0x400 \n"
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"or \\flags, $1 \n"
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"mtc0 \\flags, $2, 1 \n"
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#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
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/*
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* Slow, but doesn't suffer from a relativly unlikely race
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* condition we're having since days 1.
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*/
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" beqz \\flags, 1f \n"
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" di \n"
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" ei \n"
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"1: \n"
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#elif defined(CONFIG_CPU_MIPSR2)
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/*
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* Fast, dangerous. Life is fun, life is good.
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*/
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" mfc0 $1, $12 \n"
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" ins $1, \\flags, 0, 1 \n"
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" mtc0 $1, $12 \n"
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#else
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" mfc0 $1, $12 \n"
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" andi \\flags, 1 \n"
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" ori $1, 0x1f \n"
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" xori $1, 0x1f \n"
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" or \\flags, $1 \n"
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" mtc0 \\flags, $12 \n"
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#endif
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" irq_disable_hazard \n"
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" .set pop \n"
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" .endm \n");
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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unsigned long __tmp1;
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* SMTC kernel needs to do a software replay of queued
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* IPIs, at the cost of branch and call overhead on each
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* local_irq_restore()
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*/
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if (unlikely(!(flags & 0x0400)))
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smtc_ipi_replay();
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#endif
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__asm__ __volatile__(
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"arch_local_irq_restore\t%0"
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: "=r" (__tmp1)
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: "0" (flags)
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: "memory");
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}
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static inline void __arch_local_irq_restore(unsigned long flags)
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{
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unsigned long __tmp1;
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__asm__ __volatile__(
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"arch_local_irq_restore\t%0"
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: "=r" (__tmp1)
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: "0" (flags)
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: "memory");
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}
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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#ifdef CONFIG_MIPS_MT_SMTC
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/*
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* SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
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*/
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return flags & 0x400;
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#else
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return !(flags & 1);
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#endif
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}
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#endif
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/*
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* Do the CPU's IRQ-state tracing from assembly code.
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*/
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#ifdef CONFIG_TRACE_IRQFLAGS
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/* Reload some registers clobbered by trace_hardirqs_on */
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#ifdef CONFIG_64BIT
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# define TRACE_IRQS_RELOAD_REGS \
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LONG_L $11, PT_R11(sp); \
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LONG_L $10, PT_R10(sp); \
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LONG_L $9, PT_R9(sp); \
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LONG_L $8, PT_R8(sp); \
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LONG_L $7, PT_R7(sp); \
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LONG_L $6, PT_R6(sp); \
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LONG_L $5, PT_R5(sp); \
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LONG_L $4, PT_R4(sp); \
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LONG_L $2, PT_R2(sp)
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#else
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# define TRACE_IRQS_RELOAD_REGS \
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LONG_L $7, PT_R7(sp); \
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LONG_L $6, PT_R6(sp); \
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LONG_L $5, PT_R5(sp); \
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LONG_L $4, PT_R4(sp); \
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LONG_L $2, PT_R2(sp)
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#endif
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# define TRACE_IRQS_ON \
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CLI; /* make sure trace_hardirqs_on() is called in kernel level */ \
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jal trace_hardirqs_on
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# define TRACE_IRQS_ON_RELOAD \
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TRACE_IRQS_ON; \
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TRACE_IRQS_RELOAD_REGS
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# define TRACE_IRQS_OFF \
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jal trace_hardirqs_off
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#else
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# define TRACE_IRQS_ON
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# define TRACE_IRQS_ON_RELOAD
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# define TRACE_IRQS_OFF
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#endif
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#endif /* _ASM_IRQFLAGS_H */
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