584 lines
14 KiB
C
584 lines
14 KiB
C
/*
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* Copyright 2007 Stephane Marchesin
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drm.h"
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#include "nouveau_drv.h"
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static uint32_t nv04_graph_ctx_regs[] = {
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0x0040053c,
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0x00400544,
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0x00400540,
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0x00400548,
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NV04_PGRAPH_CTX_SWITCH1,
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NV04_PGRAPH_CTX_SWITCH2,
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NV04_PGRAPH_CTX_SWITCH3,
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NV04_PGRAPH_CTX_SWITCH4,
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NV04_PGRAPH_CTX_CACHE1,
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NV04_PGRAPH_CTX_CACHE2,
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NV04_PGRAPH_CTX_CACHE3,
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NV04_PGRAPH_CTX_CACHE4,
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0x00400184,
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0x004001a4,
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0x004001c4,
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0x004001e4,
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0x00400188,
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0x004001a8,
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0x004001c8,
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0x004001e8,
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0x0040018c,
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0x004001ac,
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0x004001cc,
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0x004001ec,
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0x00400190,
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0x004001b0,
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0x004001d0,
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0x004001f0,
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0x00400194,
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0x004001b4,
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0x004001d4,
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0x004001f4,
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0x00400198,
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0x004001b8,
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0x004001d8,
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0x004001f8,
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0x0040019c,
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0x004001bc,
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0x004001dc,
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0x004001fc,
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0x00400174,
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NV04_PGRAPH_DMA_START_0,
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NV04_PGRAPH_DMA_START_1,
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NV04_PGRAPH_DMA_LENGTH,
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NV04_PGRAPH_DMA_MISC,
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NV04_PGRAPH_DMA_PITCH,
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NV04_PGRAPH_BOFFSET0,
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NV04_PGRAPH_BBASE0,
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NV04_PGRAPH_BLIMIT0,
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NV04_PGRAPH_BOFFSET1,
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NV04_PGRAPH_BBASE1,
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NV04_PGRAPH_BLIMIT1,
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NV04_PGRAPH_BOFFSET2,
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NV04_PGRAPH_BBASE2,
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NV04_PGRAPH_BLIMIT2,
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NV04_PGRAPH_BOFFSET3,
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NV04_PGRAPH_BBASE3,
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NV04_PGRAPH_BLIMIT3,
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NV04_PGRAPH_BOFFSET4,
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NV04_PGRAPH_BBASE4,
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NV04_PGRAPH_BLIMIT4,
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NV04_PGRAPH_BOFFSET5,
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NV04_PGRAPH_BBASE5,
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NV04_PGRAPH_BLIMIT5,
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NV04_PGRAPH_BPITCH0,
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NV04_PGRAPH_BPITCH1,
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NV04_PGRAPH_BPITCH2,
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NV04_PGRAPH_BPITCH3,
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NV04_PGRAPH_BPITCH4,
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NV04_PGRAPH_SURFACE,
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NV04_PGRAPH_STATE,
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NV04_PGRAPH_BSWIZZLE2,
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NV04_PGRAPH_BSWIZZLE5,
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NV04_PGRAPH_BPIXEL,
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NV04_PGRAPH_NOTIFY,
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NV04_PGRAPH_PATT_COLOR0,
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NV04_PGRAPH_PATT_COLOR1,
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NV04_PGRAPH_PATT_COLORRAM+0x00,
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NV04_PGRAPH_PATT_COLORRAM+0x04,
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NV04_PGRAPH_PATT_COLORRAM+0x08,
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NV04_PGRAPH_PATT_COLORRAM+0x0c,
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NV04_PGRAPH_PATT_COLORRAM+0x10,
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NV04_PGRAPH_PATT_COLORRAM+0x14,
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NV04_PGRAPH_PATT_COLORRAM+0x18,
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NV04_PGRAPH_PATT_COLORRAM+0x1c,
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NV04_PGRAPH_PATT_COLORRAM+0x20,
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NV04_PGRAPH_PATT_COLORRAM+0x24,
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NV04_PGRAPH_PATT_COLORRAM+0x28,
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NV04_PGRAPH_PATT_COLORRAM+0x2c,
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NV04_PGRAPH_PATT_COLORRAM+0x30,
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NV04_PGRAPH_PATT_COLORRAM+0x34,
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NV04_PGRAPH_PATT_COLORRAM+0x38,
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NV04_PGRAPH_PATT_COLORRAM+0x3c,
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NV04_PGRAPH_PATT_COLORRAM+0x40,
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NV04_PGRAPH_PATT_COLORRAM+0x44,
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NV04_PGRAPH_PATT_COLORRAM+0x48,
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NV04_PGRAPH_PATT_COLORRAM+0x4c,
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NV04_PGRAPH_PATT_COLORRAM+0x50,
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NV04_PGRAPH_PATT_COLORRAM+0x54,
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NV04_PGRAPH_PATT_COLORRAM+0x58,
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NV04_PGRAPH_PATT_COLORRAM+0x5c,
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NV04_PGRAPH_PATT_COLORRAM+0x60,
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NV04_PGRAPH_PATT_COLORRAM+0x64,
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NV04_PGRAPH_PATT_COLORRAM+0x68,
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NV04_PGRAPH_PATT_COLORRAM+0x6c,
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NV04_PGRAPH_PATT_COLORRAM+0x70,
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NV04_PGRAPH_PATT_COLORRAM+0x74,
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NV04_PGRAPH_PATT_COLORRAM+0x78,
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NV04_PGRAPH_PATT_COLORRAM+0x7c,
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NV04_PGRAPH_PATT_COLORRAM+0x80,
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NV04_PGRAPH_PATT_COLORRAM+0x84,
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NV04_PGRAPH_PATT_COLORRAM+0x88,
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NV04_PGRAPH_PATT_COLORRAM+0x8c,
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NV04_PGRAPH_PATT_COLORRAM+0x90,
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NV04_PGRAPH_PATT_COLORRAM+0x94,
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NV04_PGRAPH_PATT_COLORRAM+0x98,
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NV04_PGRAPH_PATT_COLORRAM+0x9c,
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NV04_PGRAPH_PATT_COLORRAM+0xa0,
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NV04_PGRAPH_PATT_COLORRAM+0xa4,
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NV04_PGRAPH_PATT_COLORRAM+0xa8,
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NV04_PGRAPH_PATT_COLORRAM+0xac,
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NV04_PGRAPH_PATT_COLORRAM+0xb0,
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NV04_PGRAPH_PATT_COLORRAM+0xb4,
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NV04_PGRAPH_PATT_COLORRAM+0xb8,
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NV04_PGRAPH_PATT_COLORRAM+0xbc,
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NV04_PGRAPH_PATT_COLORRAM+0xc0,
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NV04_PGRAPH_PATT_COLORRAM+0xc4,
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NV04_PGRAPH_PATT_COLORRAM+0xc8,
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NV04_PGRAPH_PATT_COLORRAM+0xcc,
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NV04_PGRAPH_PATT_COLORRAM+0xd0,
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NV04_PGRAPH_PATT_COLORRAM+0xd4,
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NV04_PGRAPH_PATT_COLORRAM+0xd8,
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NV04_PGRAPH_PATT_COLORRAM+0xdc,
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NV04_PGRAPH_PATT_COLORRAM+0xe0,
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NV04_PGRAPH_PATT_COLORRAM+0xe4,
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NV04_PGRAPH_PATT_COLORRAM+0xe8,
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NV04_PGRAPH_PATT_COLORRAM+0xec,
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NV04_PGRAPH_PATT_COLORRAM+0xf0,
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NV04_PGRAPH_PATT_COLORRAM+0xf4,
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NV04_PGRAPH_PATT_COLORRAM+0xf8,
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NV04_PGRAPH_PATT_COLORRAM+0xfc,
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NV04_PGRAPH_PATTERN,
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0x0040080c,
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NV04_PGRAPH_PATTERN_SHAPE,
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0x00400600,
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NV04_PGRAPH_ROP3,
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NV04_PGRAPH_CHROMA,
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NV04_PGRAPH_BETA_AND,
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NV04_PGRAPH_BETA_PREMULT,
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NV04_PGRAPH_CONTROL0,
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NV04_PGRAPH_CONTROL1,
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NV04_PGRAPH_CONTROL2,
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NV04_PGRAPH_BLEND,
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NV04_PGRAPH_STORED_FMT,
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NV04_PGRAPH_SOURCE_COLOR,
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0x00400560,
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0x00400568,
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0x00400564,
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0x0040056c,
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0x00400400,
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0x00400480,
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0x00400404,
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0x00400484,
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0x00400408,
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0x00400488,
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0x0040040c,
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0x0040048c,
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0x00400410,
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0x00400490,
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0x00400414,
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0x00400494,
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0x00400418,
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0x00400498,
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0x0040041c,
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0x0040049c,
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0x00400420,
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0x004004a0,
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0x00400424,
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0x004004a4,
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0x00400428,
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0x004004a8,
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0x0040042c,
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0x004004ac,
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0x00400430,
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0x004004b0,
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0x00400434,
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0x004004b4,
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0x00400438,
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0x004004b8,
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0x0040043c,
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0x004004bc,
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0x00400440,
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0x004004c0,
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0x00400444,
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0x004004c4,
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0x00400448,
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0x004004c8,
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0x0040044c,
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0x004004cc,
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0x00400450,
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0x004004d0,
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0x00400454,
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0x004004d4,
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0x00400458,
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0x004004d8,
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0x0040045c,
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0x004004dc,
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0x00400460,
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0x004004e0,
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0x00400464,
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0x004004e4,
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0x00400468,
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0x004004e8,
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0x0040046c,
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0x004004ec,
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0x00400470,
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0x004004f0,
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0x00400474,
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0x004004f4,
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0x00400478,
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0x004004f8,
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0x0040047c,
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0x004004fc,
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0x00400534,
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0x00400538,
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0x00400514,
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0x00400518,
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0x0040051c,
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0x00400520,
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0x00400524,
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0x00400528,
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0x0040052c,
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0x00400530,
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0x00400d00,
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0x00400d40,
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0x00400d80,
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0x00400d04,
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0x00400d44,
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0x00400d84,
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0x00400d08,
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0x00400d48,
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0x00400d88,
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0x00400d0c,
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0x00400d4c,
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0x00400d8c,
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0x00400d10,
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0x00400d50,
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0x00400d90,
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0x00400d14,
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0x00400d54,
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0x00400d94,
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0x00400d18,
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0x00400d58,
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0x00400d98,
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0x00400d1c,
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0x00400d5c,
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0x00400d9c,
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0x00400d20,
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0x00400d60,
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0x00400da0,
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0x00400d24,
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0x00400d64,
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0x00400da4,
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0x00400d28,
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0x00400d68,
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0x00400da8,
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0x00400d2c,
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0x00400d6c,
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0x00400dac,
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0x00400d30,
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0x00400d70,
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0x00400db0,
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0x00400d34,
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0x00400d74,
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0x00400db4,
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0x00400d38,
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0x00400d78,
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0x00400db8,
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0x00400d3c,
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0x00400d7c,
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0x00400dbc,
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0x00400590,
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0x00400594,
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0x00400598,
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0x0040059c,
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0x004005a8,
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0x004005ac,
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0x004005b0,
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0x004005b4,
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0x004005c0,
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0x004005c4,
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0x004005c8,
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0x004005cc,
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0x004005d0,
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0x004005d4,
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0x004005d8,
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0x004005dc,
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0x004005e0,
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NV04_PGRAPH_PASSTHRU_0,
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NV04_PGRAPH_PASSTHRU_1,
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NV04_PGRAPH_PASSTHRU_2,
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NV04_PGRAPH_DVD_COLORFMT,
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NV04_PGRAPH_SCALED_FORMAT,
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NV04_PGRAPH_MISC24_0,
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NV04_PGRAPH_MISC24_1,
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NV04_PGRAPH_MISC24_2,
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0x00400500,
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0x00400504,
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NV04_PGRAPH_VALID1,
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NV04_PGRAPH_VALID2,
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NV04_PGRAPH_DEBUG_3
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};
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struct graph_state {
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int nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
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};
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struct nouveau_channel *
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nv04_graph_channel(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int chid = dev_priv->engine.fifo.channels;
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if (nv_rd32(dev, NV04_PGRAPH_CTX_CONTROL) & 0x00010000)
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chid = nv_rd32(dev, NV04_PGRAPH_CTX_USER) >> 24;
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if (chid >= dev_priv->engine.fifo.channels)
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return NULL;
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return dev_priv->fifos[chid];
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}
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void
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nv04_graph_context_switch(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_channel *chan = NULL;
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int chid;
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pgraph->fifo_access(dev, false);
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nouveau_wait_for_idle(dev);
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/* If previous context is valid, we need to save it */
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pgraph->unload_context(dev);
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/* Load context for next channel */
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chid = dev_priv->engine.fifo.channel_id(dev);
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chan = dev_priv->fifos[chid];
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if (chan)
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nv04_graph_load_context(chan);
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pgraph->fifo_access(dev, true);
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}
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static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
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if (nv04_graph_ctx_regs[i] == reg)
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return &ctx->nv04[i];
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}
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return NULL;
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}
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int nv04_graph_create_context(struct nouveau_channel *chan)
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{
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struct graph_state *pgraph_ctx;
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NV_DEBUG(chan->dev, "nv04_graph_context_create %d\n", chan->id);
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chan->pgraph_ctx = pgraph_ctx = kzalloc(sizeof(*pgraph_ctx),
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GFP_KERNEL);
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if (pgraph_ctx == NULL)
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return -ENOMEM;
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|
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*ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
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return 0;
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}
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|
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void nv04_graph_destroy_context(struct nouveau_channel *chan)
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{
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struct graph_state *pgraph_ctx = chan->pgraph_ctx;
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|
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kfree(pgraph_ctx);
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chan->pgraph_ctx = NULL;
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}
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|
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int nv04_graph_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct graph_state *pgraph_ctx = chan->pgraph_ctx;
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uint32_t tmp;
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int i;
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|
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for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
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nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
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nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
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tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
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nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp | chan->id << 24);
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tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2);
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nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff);
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return 0;
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}
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|
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int
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nv04_graph_unload_context(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_channel *chan = NULL;
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struct graph_state *ctx;
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uint32_t tmp;
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int i;
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chan = pgraph->channel(dev);
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if (!chan)
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return 0;
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ctx = chan->pgraph_ctx;
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for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
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ctx->nv04[i] = nv_rd32(dev, nv04_graph_ctx_regs[i]);
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|
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nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
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tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
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tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
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nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
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return 0;
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}
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|
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int nv04_graph_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t tmp;
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
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~NV_PMC_ENABLE_PGRAPH);
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
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NV_PMC_ENABLE_PGRAPH);
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/* Enable PGRAPH interrupts */
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nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF);
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nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
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nv_wr32(dev, NV04_PGRAPH_VALID1, 0);
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nv_wr32(dev, NV04_PGRAPH_VALID2, 0);
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/*nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x000001FF);
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nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
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nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x1231c000);
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/*1231C000 blob, 001 haiku*/
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//*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
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nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x72111100);
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/*0x72111100 blob , 01 haiku*/
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/*nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
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nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
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/*haiku same*/
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/*nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
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nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
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/*haiku and blob 10d4*/
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nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF);
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nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
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tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
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tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
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nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
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/* These don't belong here, they're part of a per-channel context */
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nv_wr32(dev, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
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nv_wr32(dev, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
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return 0;
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}
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void nv04_graph_takedown(struct drm_device *dev)
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{
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}
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void
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nv04_graph_fifo_access(struct drm_device *dev, bool enabled)
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{
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if (enabled)
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nv_wr32(dev, NV04_PGRAPH_FIFO,
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nv_rd32(dev, NV04_PGRAPH_FIFO) | 1);
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else
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nv_wr32(dev, NV04_PGRAPH_FIFO,
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nv_rd32(dev, NV04_PGRAPH_FIFO) & ~1);
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}
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static int
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nv04_graph_mthd_set_ref(struct nouveau_channel *chan, int grclass,
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int mthd, uint32_t data)
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{
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chan->fence.last_sequence_irq = data;
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nouveau_fence_handler(chan->dev, chan->id);
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return 0;
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}
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static int
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nv04_graph_mthd_set_operation(struct nouveau_channel *chan, int grclass,
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int mthd, uint32_t data)
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{
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struct drm_device *dev = chan->dev;
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uint32_t instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
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int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
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uint32_t tmp;
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tmp = nv_ri32(dev, instance);
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tmp &= ~0x00038000;
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tmp |= ((data & 7) << 15);
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nv_wi32(dev, instance, tmp);
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nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp);
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nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
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return 0;
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}
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static struct nouveau_pgraph_object_method nv04_graph_mthds_sw[] = {
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{ 0x0150, nv04_graph_mthd_set_ref },
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{}
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};
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static struct nouveau_pgraph_object_method nv04_graph_mthds_set_operation[] = {
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{ 0x02fc, nv04_graph_mthd_set_operation },
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{},
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};
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struct nouveau_pgraph_object_class nv04_graph_grclass[] = {
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{ 0x0039, false, NULL },
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{ 0x004a, false, nv04_graph_mthds_set_operation }, /* gdirect */
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{ 0x005f, false, nv04_graph_mthds_set_operation }, /* imageblit */
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{ 0x0061, false, nv04_graph_mthds_set_operation }, /* ifc */
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{ 0x0077, false, nv04_graph_mthds_set_operation }, /* sifm */
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{ 0x0030, false, NULL }, /* null */
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{ 0x0042, false, NULL }, /* surf2d */
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{ 0x0043, false, NULL }, /* rop */
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{ 0x0012, false, NULL }, /* beta1 */
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{ 0x0072, false, NULL }, /* beta4 */
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{ 0x0019, false, NULL }, /* cliprect */
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{ 0x0044, false, NULL }, /* pattern */
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{ 0x0052, false, NULL }, /* swzsurf */
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{ 0x0053, false, NULL }, /* surf3d */
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{ 0x0054, false, NULL }, /* tex_tri */
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{ 0x0055, false, NULL }, /* multitex_tri */
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{ 0x506e, true, nv04_graph_mthds_sw },
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{}
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};
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