f411fade00
Initial support for the r8a7779 SoC and the Marzen board (V2). Only SCIF ports and the TMU are supported at this point. To keep things simple only entity-mapped virt-to-phys mappings are supported. This forces drivers and other SoC glue code to make use of ioremap(). We cannot support early serial console due to virtual address space collisions with the ARM kernel. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
58 lines
1.8 KiB
C
58 lines
1.8 KiB
C
/*
|
|
* r8a7779 processor support - INTC hardware block
|
|
*
|
|
* Copyright (C) 2011 Renesas Solutions Corp.
|
|
* Copyright (C) 2011 Magnus Damm
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
|
*/
|
|
#include <linux/kernel.h>
|
|
#include <linux/init.h>
|
|
#include <linux/interrupt.h>
|
|
#include <linux/irq.h>
|
|
#include <linux/io.h>
|
|
#include <mach/common.h>
|
|
#include <mach/intc.h>
|
|
#include <mach/r8a7779.h>
|
|
#include <asm/hardware/gic.h>
|
|
#include <asm/mach-types.h>
|
|
#include <asm/mach/arch.h>
|
|
|
|
#define INT2SMSKCR0 0xfe7822a0
|
|
#define INT2SMSKCR1 0xfe7822a4
|
|
#define INT2SMSKCR2 0xfe7822a8
|
|
#define INT2SMSKCR3 0xfe7822ac
|
|
#define INT2SMSKCR4 0xfe7822b0
|
|
|
|
static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
|
|
{
|
|
return 0; /* always allow wakeup */
|
|
}
|
|
|
|
void __init r8a7779_init_irq(void)
|
|
{
|
|
void __iomem *gic_dist_base = __io(0xf0001000);
|
|
void __iomem *gic_cpu_base = __io(0xf0000100);
|
|
|
|
/* use GIC to handle interrupts */
|
|
gic_init(0, 29, gic_dist_base, gic_cpu_base);
|
|
gic_arch_extn.irq_set_wake = r8a7779_set_wake;
|
|
|
|
/* unmask all known interrupts in INTCS2 */
|
|
__raw_writel(0xfffffff0, INT2SMSKCR0);
|
|
__raw_writel(0xfff7ffff, INT2SMSKCR1);
|
|
__raw_writel(0xfffbffdf, INT2SMSKCR2);
|
|
__raw_writel(0xbffffffc, INT2SMSKCR3);
|
|
__raw_writel(0x003fee3f, INT2SMSKCR4);
|
|
}
|