3ce06a320f
New revision of netxen chip has 2MB PCI memory. Older chips had 128MB addressable PCI memory. To retain compatibility, this patch adds function pointers based on pci bar0 size. Signed-off-by: Dhananjay Phadke <dhananjay@netxen.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
507 lines
17 KiB
C
507 lines
17 KiB
C
/*
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* Copyright (C) 2003 - 2006 NetXen, Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston,
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* MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.
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*
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* Contact Information:
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* info@netxen.com
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* NetXen,
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* 3965 Freedom Circle, Fourth floor,
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* Santa Clara, CA 95054
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*
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*
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* Structures, enums, and macros for the MAC
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*
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*/
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#ifndef __NETXEN_NIC_HW_H_
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#define __NETXEN_NIC_HW_H_
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#include "netxen_nic_hdr.h"
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/* Hardware memory size of 128 meg */
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#define NETXEN_MEMADDR_MAX (128 * 1024 * 1024)
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#ifndef readq
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static inline u64 readq(void __iomem * addr)
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{
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return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
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}
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#endif
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#ifndef writeq
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static inline void writeq(u64 val, void __iomem * addr)
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{
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writel(((u32) (val)), (addr));
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writel(((u32) (val >> 32)), (addr + 4));
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}
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#endif
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static inline void netxen_nic_hw_block_write64(u64 __iomem * data_ptr,
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u64 __iomem * addr,
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int num_words)
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{
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int num;
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for (num = 0; num < num_words; num++) {
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writeq(readq((void __iomem *)data_ptr), addr);
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addr++;
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data_ptr++;
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}
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}
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static inline void netxen_nic_hw_block_read64(u64 __iomem * data_ptr,
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u64 __iomem * addr, int num_words)
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{
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int num;
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for (num = 0; num < num_words; num++) {
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writeq(readq((void __iomem *)addr), data_ptr);
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addr++;
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data_ptr++;
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}
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}
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struct netxen_adapter;
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#define NETXEN_PCI_MAPSIZE_BYTES (NETXEN_PCI_MAPSIZE << 20)
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struct netxen_port;
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void netxen_nic_set_link_parameters(struct netxen_adapter *adapter);
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void netxen_nic_flash_print(struct netxen_adapter *adapter);
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typedef u8 netxen_ethernet_macaddr_t[6];
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/* Nibble or Byte mode for phy interface (GbE mode only) */
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typedef enum {
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NETXEN_NIU_10_100_MB = 0,
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NETXEN_NIU_1000_MB
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} netxen_niu_gbe_ifmode_t;
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#define _netxen_crb_get_bit(var, bit) ((var >> bit) & 0x1)
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/*
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* NIU GB MAC Config Register 0 (applies to GB0, GB1, GB2, GB3)
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*
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* Bit 0 : enable_tx => 1:enable frame xmit, 0:disable
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* Bit 1 : tx_synced => R/O: xmit enable synched to xmit stream
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* Bit 2 : enable_rx => 1:enable frame recv, 0:disable
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* Bit 3 : rx_synced => R/O: recv enable synched to recv stream
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* Bit 4 : tx_flowctl => 1:enable pause frame generation, 0:disable
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* Bit 5 : rx_flowctl => 1:act on recv'd pause frames, 0:ignore
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* Bit 8 : loopback => 1:loop MAC xmits to MAC recvs, 0:normal
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* Bit 16: tx_reset_pb => 1:reset frame xmit protocol blk, 0:no-op
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* Bit 17: rx_reset_pb => 1:reset frame recv protocol blk, 0:no-op
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* Bit 18: tx_reset_mac => 1:reset data/ctl multiplexer blk, 0:no-op
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* Bit 19: rx_reset_mac => 1:reset ctl frames & timers blk, 0:no-op
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* Bit 31: soft_reset => 1:reset the MAC and the SERDES, 0:no-op
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*/
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#define netxen_gb_enable_tx(config_word) \
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((config_word) |= 1 << 0)
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#define netxen_gb_enable_rx(config_word) \
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((config_word) |= 1 << 2)
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#define netxen_gb_tx_flowctl(config_word) \
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((config_word) |= 1 << 4)
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#define netxen_gb_rx_flowctl(config_word) \
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((config_word) |= 1 << 5)
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#define netxen_gb_tx_reset_pb(config_word) \
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((config_word) |= 1 << 16)
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#define netxen_gb_rx_reset_pb(config_word) \
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((config_word) |= 1 << 17)
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#define netxen_gb_tx_reset_mac(config_word) \
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((config_word) |= 1 << 18)
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#define netxen_gb_rx_reset_mac(config_word) \
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((config_word) |= 1 << 19)
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#define netxen_gb_soft_reset(config_word) \
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((config_word) |= 1 << 31)
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#define netxen_gb_unset_tx_flowctl(config_word) \
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((config_word) &= ~(1 << 4))
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#define netxen_gb_unset_rx_flowctl(config_word) \
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((config_word) &= ~(1 << 5))
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#define netxen_gb_get_tx_synced(config_word) \
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_netxen_crb_get_bit((config_word), 1)
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#define netxen_gb_get_rx_synced(config_word) \
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_netxen_crb_get_bit((config_word), 3)
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#define netxen_gb_get_tx_flowctl(config_word) \
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_netxen_crb_get_bit((config_word), 4)
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#define netxen_gb_get_rx_flowctl(config_word) \
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_netxen_crb_get_bit((config_word), 5)
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#define netxen_gb_get_soft_reset(config_word) \
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_netxen_crb_get_bit((config_word), 31)
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/*
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* NIU GB MAC Config Register 1 (applies to GB0, GB1, GB2, GB3)
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*
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* Bit 0 : duplex => 1:full duplex mode, 0:half duplex
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* Bit 1 : crc_enable => 1:append CRC to xmit frames, 0:dont append
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* Bit 2 : padshort => 1:pad short frames and add CRC, 0:dont pad
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* Bit 4 : checklength => 1:check framelen with actual,0:dont check
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* Bit 5 : hugeframes => 1:allow oversize xmit frames, 0:dont allow
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* Bits 8-9 : intfmode => 01:nibble (10/100), 10:byte (1000)
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* Bits 12-15 : preamblelen => preamble field length in bytes, default 7
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*/
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#define netxen_gb_set_duplex(config_word) \
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((config_word) |= 1 << 0)
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#define netxen_gb_set_crc_enable(config_word) \
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((config_word) |= 1 << 1)
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#define netxen_gb_set_padshort(config_word) \
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((config_word) |= 1 << 2)
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#define netxen_gb_set_checklength(config_word) \
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((config_word) |= 1 << 4)
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#define netxen_gb_set_hugeframes(config_word) \
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((config_word) |= 1 << 5)
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#define netxen_gb_set_preamblelen(config_word, val) \
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((config_word) |= ((val) << 12) & 0xF000)
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#define netxen_gb_set_intfmode(config_word, val) \
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((config_word) |= ((val) << 8) & 0x300)
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#define netxen_gb_get_stationaddress_low(config_word) ((config_word) >> 16)
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#define netxen_gb_set_mii_mgmt_clockselect(config_word, val) \
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((config_word) |= ((val) & 0x07))
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#define netxen_gb_mii_mgmt_reset(config_word) \
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((config_word) |= 1 << 31)
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#define netxen_gb_mii_mgmt_unset(config_word) \
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((config_word) &= ~(1 << 31))
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/*
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* NIU GB MII Mgmt Command Register (applies to GB0, GB1, GB2, GB3)
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* Bit 0 : read_cycle => 1:perform single read cycle, 0:no-op
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* Bit 1 : scan_cycle => 1:perform continuous read cycles, 0:no-op
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*/
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#define netxen_gb_mii_mgmt_set_read_cycle(config_word) \
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((config_word) |= 1 << 0)
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#define netxen_gb_mii_mgmt_reg_addr(config_word, val) \
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((config_word) |= ((val) & 0x1F))
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#define netxen_gb_mii_mgmt_phy_addr(config_word, val) \
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((config_word) |= (((val) & 0x1F) << 8))
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/*
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* NIU GB MII Mgmt Indicators Register (applies to GB0, GB1, GB2, GB3)
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* Read-only register.
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* Bit 0 : busy => 1:performing an MII mgmt cycle, 0:idle
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* Bit 1 : scanning => 1:scan operation in progress, 0:idle
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* Bit 2 : notvalid => :mgmt result data not yet valid, 0:idle
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*/
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#define netxen_get_gb_mii_mgmt_busy(config_word) \
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_netxen_crb_get_bit(config_word, 0)
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#define netxen_get_gb_mii_mgmt_scanning(config_word) \
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_netxen_crb_get_bit(config_word, 1)
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#define netxen_get_gb_mii_mgmt_notvalid(config_word) \
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_netxen_crb_get_bit(config_word, 2)
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/*
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* NIU XG Pause Ctl Register
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*
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* Bit 0 : xg0_mask => 1:disable tx pause frames
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* Bit 1 : xg0_request => 1:request single pause frame
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* Bit 2 : xg0_on_off => 1:request is pause on, 0:off
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* Bit 3 : xg1_mask => 1:disable tx pause frames
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* Bit 4 : xg1_request => 1:request single pause frame
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* Bit 5 : xg1_on_off => 1:request is pause on, 0:off
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*/
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#define netxen_xg_set_xg0_mask(config_word) \
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((config_word) |= 1 << 0)
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#define netxen_xg_set_xg1_mask(config_word) \
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((config_word) |= 1 << 3)
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#define netxen_xg_get_xg0_mask(config_word) \
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_netxen_crb_get_bit((config_word), 0)
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#define netxen_xg_get_xg1_mask(config_word) \
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_netxen_crb_get_bit((config_word), 3)
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#define netxen_xg_unset_xg0_mask(config_word) \
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((config_word) &= ~(1 << 0))
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#define netxen_xg_unset_xg1_mask(config_word) \
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((config_word) &= ~(1 << 3))
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/*
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* NIU XG Pause Ctl Register
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*
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* Bit 0 : xg0_mask => 1:disable tx pause frames
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* Bit 1 : xg0_request => 1:request single pause frame
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* Bit 2 : xg0_on_off => 1:request is pause on, 0:off
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* Bit 3 : xg1_mask => 1:disable tx pause frames
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* Bit 4 : xg1_request => 1:request single pause frame
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* Bit 5 : xg1_on_off => 1:request is pause on, 0:off
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*/
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#define netxen_gb_set_gb0_mask(config_word) \
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((config_word) |= 1 << 0)
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#define netxen_gb_set_gb1_mask(config_word) \
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((config_word) |= 1 << 2)
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#define netxen_gb_set_gb2_mask(config_word) \
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((config_word) |= 1 << 4)
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#define netxen_gb_set_gb3_mask(config_word) \
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((config_word) |= 1 << 6)
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#define netxen_gb_get_gb0_mask(config_word) \
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_netxen_crb_get_bit((config_word), 0)
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#define netxen_gb_get_gb1_mask(config_word) \
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_netxen_crb_get_bit((config_word), 2)
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#define netxen_gb_get_gb2_mask(config_word) \
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_netxen_crb_get_bit((config_word), 4)
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#define netxen_gb_get_gb3_mask(config_word) \
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_netxen_crb_get_bit((config_word), 6)
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#define netxen_gb_unset_gb0_mask(config_word) \
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((config_word) &= ~(1 << 0))
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#define netxen_gb_unset_gb1_mask(config_word) \
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((config_word) &= ~(1 << 2))
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#define netxen_gb_unset_gb2_mask(config_word) \
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((config_word) &= ~(1 << 4))
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#define netxen_gb_unset_gb3_mask(config_word) \
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((config_word) &= ~(1 << 6))
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/*
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* PHY-Specific MII control/status registers.
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*/
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typedef enum {
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NETXEN_NIU_GB_MII_MGMT_ADDR_CONTROL = 0,
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NETXEN_NIU_GB_MII_MGMT_ADDR_STATUS = 1,
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NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_0 = 2,
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NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_ID_1 = 3,
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NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG = 4,
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NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART = 5,
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NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG_MORE = 6,
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NETXEN_NIU_GB_MII_MGMT_ADDR_NEXTPAGE_XMIT = 7,
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NETXEN_NIU_GB_MII_MGMT_ADDR_LNKPART_NEXTPAGE = 8,
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NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_CONTROL = 9,
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NETXEN_NIU_GB_MII_MGMT_ADDR_1000BT_STATUS = 10,
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NETXEN_NIU_GB_MII_MGMT_ADDR_EXTENDED_STATUS = 15,
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NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL = 16,
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NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS = 17,
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NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE = 18,
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NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS = 19,
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NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE = 20,
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NETXEN_NIU_GB_MII_MGMT_ADDR_RECV_ERROR_COUNT = 21,
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NETXEN_NIU_GB_MII_MGMT_ADDR_LED_CONTROL = 24,
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NETXEN_NIU_GB_MII_MGMT_ADDR_LED_OVERRIDE = 25,
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NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_CONTROL_MORE_YET = 26,
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NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS_MORE = 27
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} netxen_niu_phy_register_t;
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/*
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* PHY-Specific Status Register (reg 17).
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*
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* Bit 0 : jabber => 1:jabber detected, 0:not
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* Bit 1 : polarity => 1:polarity reversed, 0:normal
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* Bit 2 : recvpause => 1:receive pause enabled, 0:disabled
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* Bit 3 : xmitpause => 1:transmit pause enabled, 0:disabled
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* Bit 4 : energydetect => 1:sleep, 0:active
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* Bit 5 : downshift => 1:downshift, 0:no downshift
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* Bit 6 : crossover => 1:MDIX (crossover), 0:MDI (no crossover)
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* Bits 7-9 : cablelen => not valid in 10Mb/s mode
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* 0:<50m, 1:50-80m, 2:80-110m, 3:110-140m, 4:>140m
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* Bit 10 : link => 1:link up, 0:link down
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* Bit 11 : resolved => 1:speed and duplex resolved, 0:not yet
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* Bit 12 : pagercvd => 1:page received, 0:page not received
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* Bit 13 : duplex => 1:full duplex, 0:half duplex
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* Bits 14-15 : speed => 0:10Mb/s, 1:100Mb/s, 2:1000Mb/s, 3:rsvd
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*/
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#define netxen_get_phy_cablelen(config_word) (((config_word) >> 7) & 0x07)
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#define netxen_get_phy_speed(config_word) (((config_word) >> 14) & 0x03)
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#define netxen_set_phy_speed(config_word, val) \
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((config_word) |= ((val & 0x03) << 14))
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#define netxen_set_phy_duplex(config_word) \
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((config_word) |= 1 << 13)
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#define netxen_clear_phy_duplex(config_word) \
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((config_word) &= ~(1 << 13))
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#define netxen_get_phy_jabber(config_word) \
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_netxen_crb_get_bit(config_word, 0)
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#define netxen_get_phy_polarity(config_word) \
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_netxen_crb_get_bit(config_word, 1)
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#define netxen_get_phy_recvpause(config_word) \
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_netxen_crb_get_bit(config_word, 2)
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#define netxen_get_phy_xmitpause(config_word) \
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_netxen_crb_get_bit(config_word, 3)
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#define netxen_get_phy_energydetect(config_word) \
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_netxen_crb_get_bit(config_word, 4)
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#define netxen_get_phy_downshift(config_word) \
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_netxen_crb_get_bit(config_word, 5)
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#define netxen_get_phy_crossover(config_word) \
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_netxen_crb_get_bit(config_word, 6)
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#define netxen_get_phy_link(config_word) \
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_netxen_crb_get_bit(config_word, 10)
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#define netxen_get_phy_resolved(config_word) \
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_netxen_crb_get_bit(config_word, 11)
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#define netxen_get_phy_pagercvd(config_word) \
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_netxen_crb_get_bit(config_word, 12)
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#define netxen_get_phy_duplex(config_word) \
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_netxen_crb_get_bit(config_word, 13)
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/*
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* Interrupt Register definition
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* This definition applies to registers 18 and 19 (int enable and int status).
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* Bit 0 : jabber
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* Bit 1 : polarity_changed
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* Bit 4 : energy_detect
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* Bit 5 : downshift
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* Bit 6 : mdi_xover_changed
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* Bit 7 : fifo_over_underflow
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* Bit 8 : false_carrier
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* Bit 9 : symbol_error
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* Bit 10: link_status_changed
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* Bit 11: autoneg_completed
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* Bit 12: page_received
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* Bit 13: duplex_changed
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* Bit 14: speed_changed
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* Bit 15: autoneg_error
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*/
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#define netxen_get_phy_int_jabber(config_word) \
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_netxen_crb_get_bit(config_word, 0)
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#define netxen_get_phy_int_polarity_changed(config_word) \
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_netxen_crb_get_bit(config_word, 1)
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#define netxen_get_phy_int_energy_detect(config_word) \
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_netxen_crb_get_bit(config_word, 4)
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#define netxen_get_phy_int_downshift(config_word) \
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_netxen_crb_get_bit(config_word, 5)
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#define netxen_get_phy_int_mdi_xover_changed(config_word) \
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_netxen_crb_get_bit(config_word, 6)
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#define netxen_get_phy_int_fifo_over_underflow(config_word) \
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_netxen_crb_get_bit(config_word, 7)
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#define netxen_get_phy_int_false_carrier(config_word) \
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_netxen_crb_get_bit(config_word, 8)
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#define netxen_get_phy_int_symbol_error(config_word) \
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_netxen_crb_get_bit(config_word, 9)
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#define netxen_get_phy_int_link_status_changed(config_word) \
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_netxen_crb_get_bit(config_word, 10)
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#define netxen_get_phy_int_autoneg_completed(config_word) \
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_netxen_crb_get_bit(config_word, 11)
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#define netxen_get_phy_int_page_received(config_word) \
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_netxen_crb_get_bit(config_word, 12)
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#define netxen_get_phy_int_duplex_changed(config_word) \
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_netxen_crb_get_bit(config_word, 13)
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#define netxen_get_phy_int_speed_changed(config_word) \
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_netxen_crb_get_bit(config_word, 14)
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#define netxen_get_phy_int_autoneg_error(config_word) \
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_netxen_crb_get_bit(config_word, 15)
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|
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#define netxen_set_phy_int_link_status_changed(config_word) \
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((config_word) |= 1 << 10)
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#define netxen_set_phy_int_autoneg_completed(config_word) \
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((config_word) |= 1 << 11)
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#define netxen_set_phy_int_speed_changed(config_word) \
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((config_word) |= 1 << 14)
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|
|
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/*
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* NIU Mode Register.
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* Bit 0 : enable FibreChannel
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* Bit 1 : enable 10/100/1000 Ethernet
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|
* Bit 2 : enable 10Gb Ethernet
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*/
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|
|
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#define netxen_get_niu_enable_ge(config_word) \
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_netxen_crb_get_bit(config_word, 1)
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|
|
|
/* Promiscous mode options (GbE mode only) */
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|
typedef enum {
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NETXEN_NIU_PROMISC_MODE = 0,
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NETXEN_NIU_NON_PROMISC_MODE,
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NETXEN_NIU_ALLMULTI_MODE
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} netxen_niu_prom_mode_t;
|
|
|
|
/*
|
|
* NIU GB Drop CRC Register
|
|
*
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|
* Bit 0 : drop_gb0 => 1:drop pkts with bad CRCs, 0:pass them on
|
|
* Bit 1 : drop_gb1 => 1:drop pkts with bad CRCs, 0:pass them on
|
|
* Bit 2 : drop_gb2 => 1:drop pkts with bad CRCs, 0:pass them on
|
|
* Bit 3 : drop_gb3 => 1:drop pkts with bad CRCs, 0:pass them on
|
|
*/
|
|
|
|
#define netxen_set_gb_drop_gb0(config_word) \
|
|
((config_word) |= 1 << 0)
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|
#define netxen_set_gb_drop_gb1(config_word) \
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|
((config_word) |= 1 << 1)
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|
#define netxen_set_gb_drop_gb2(config_word) \
|
|
((config_word) |= 1 << 2)
|
|
#define netxen_set_gb_drop_gb3(config_word) \
|
|
((config_word) |= 1 << 3)
|
|
|
|
#define netxen_clear_gb_drop_gb0(config_word) \
|
|
((config_word) &= ~(1 << 0))
|
|
#define netxen_clear_gb_drop_gb1(config_word) \
|
|
((config_word) &= ~(1 << 1))
|
|
#define netxen_clear_gb_drop_gb2(config_word) \
|
|
((config_word) &= ~(1 << 2))
|
|
#define netxen_clear_gb_drop_gb3(config_word) \
|
|
((config_word) &= ~(1 << 3))
|
|
|
|
/*
|
|
* NIU XG MAC Config Register
|
|
*
|
|
* Bit 0 : tx_enable => 1:enable frame xmit, 0:disable
|
|
* Bit 2 : rx_enable => 1:enable frame recv, 0:disable
|
|
* Bit 4 : soft_reset => 1:reset the MAC , 0:no-op
|
|
* Bit 27: xaui_framer_reset
|
|
* Bit 28: xaui_rx_reset
|
|
* Bit 29: xaui_tx_reset
|
|
* Bit 30: xg_ingress_afifo_reset
|
|
* Bit 31: xg_egress_afifo_reset
|
|
*/
|
|
|
|
#define netxen_xg_soft_reset(config_word) \
|
|
((config_word) |= 1 << 4)
|
|
|
|
/* Set promiscuous mode for a GbE interface */
|
|
int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
|
|
netxen_niu_prom_mode_t mode);
|
|
int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
|
|
netxen_niu_prom_mode_t mode);
|
|
|
|
/* set the MAC address for a given MAC */
|
|
int netxen_niu_macaddr_set(struct netxen_adapter *adapter,
|
|
netxen_ethernet_macaddr_t addr);
|
|
|
|
/* XG version */
|
|
int netxen_niu_xg_macaddr_set(struct netxen_adapter *adapter,
|
|
netxen_ethernet_macaddr_t addr);
|
|
|
|
/* Generic enable for GbE ports. Will detect the speed of the link. */
|
|
int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port);
|
|
|
|
int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port);
|
|
|
|
/* Disable a GbE interface */
|
|
int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter);
|
|
|
|
int netxen_niu_disable_xg_port(struct netxen_adapter *adapter);
|
|
|
|
typedef struct {
|
|
unsigned valid;
|
|
unsigned start_128M;
|
|
unsigned end_128M;
|
|
unsigned start_2M;
|
|
} crb_128M_2M_sub_block_map_t;
|
|
|
|
typedef struct {
|
|
crb_128M_2M_sub_block_map_t sub_block[16];
|
|
} crb_128M_2M_block_map_t;
|
|
|
|
#endif /* __NETXEN_NIC_HW_H_ */
|