374 lines
8.4 KiB
C
374 lines
8.4 KiB
C
/*
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* linux/arch/arm/mach-integrator/core.c
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*
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* Copyright (C) 2000-2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/termios.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/serial.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <asm/clkdev.h>
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#include <mach/clkdev.h>
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#include <mach/hardware.h>
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#include <mach/platform.h>
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#include <asm/irq.h>
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#include <asm/hardware/arm_timer.h>
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#include <mach/cm.h>
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#include <asm/system.h>
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#include <asm/leds.h>
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#include <asm/mach/time.h>
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#include "common.h"
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static struct amba_pl010_data integrator_uart_data;
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static struct amba_device rtc_device = {
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.dev = {
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.init_name = "mb:15",
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},
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.res = {
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.start = INTEGRATOR_RTC_BASE,
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.end = INTEGRATOR_RTC_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_RTCINT, NO_IRQ },
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.periphid = 0x00041030,
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};
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static struct amba_device uart0_device = {
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.dev = {
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.init_name = "mb:16",
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.platform_data = &integrator_uart_data,
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},
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.res = {
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.start = INTEGRATOR_UART0_BASE,
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.end = INTEGRATOR_UART0_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_UARTINT0, NO_IRQ },
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.periphid = 0x0041010,
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};
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static struct amba_device uart1_device = {
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.dev = {
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.init_name = "mb:17",
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.platform_data = &integrator_uart_data,
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},
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.res = {
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.start = INTEGRATOR_UART1_BASE,
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.end = INTEGRATOR_UART1_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_UARTINT1, NO_IRQ },
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.periphid = 0x0041010,
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};
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static struct amba_device kmi0_device = {
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.dev = {
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.init_name = "mb:18",
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},
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.res = {
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.start = KMI0_BASE,
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.end = KMI0_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_KMIINT0, NO_IRQ },
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.periphid = 0x00041050,
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};
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static struct amba_device kmi1_device = {
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.dev = {
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.init_name = "mb:19",
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},
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.res = {
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.start = KMI1_BASE,
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.end = KMI1_BASE + SZ_4K - 1,
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.flags = IORESOURCE_MEM,
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},
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.irq = { IRQ_KMIINT1, NO_IRQ },
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.periphid = 0x00041050,
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};
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static struct amba_device *amba_devs[] __initdata = {
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&rtc_device,
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&uart0_device,
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&uart1_device,
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&kmi0_device,
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&kmi1_device,
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};
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/*
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* These are fixed clocks.
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*/
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static struct clk clk24mhz = {
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.rate = 24000000,
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};
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static struct clk uartclk = {
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.rate = 14745600,
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};
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static struct clk_lookup lookups[] = {
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{ /* UART0 */
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.dev_id = "mb:16",
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.clk = &uartclk,
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}, { /* UART1 */
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.dev_id = "mb:17",
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.clk = &uartclk,
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}, { /* KMI0 */
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.dev_id = "mb:18",
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.clk = &clk24mhz,
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}, { /* KMI1 */
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.dev_id = "mb:19",
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.clk = &clk24mhz,
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}, { /* MMCI - IntegratorCP */
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.dev_id = "mb:1c",
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.clk = &uartclk,
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}
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};
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static int __init integrator_init(void)
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{
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int i;
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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amba_device_register(d, &iomem_resource);
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}
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return 0;
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}
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arch_initcall(integrator_init);
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/*
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* On the Integrator platform, the port RTS and DTR are provided by
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* bits in the following SC_CTRLS register bits:
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* RTS DTR
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* UART0 7 6
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* UART1 5 4
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*/
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#define SC_CTRLC (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLC_OFFSET)
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#define SC_CTRLS (IO_ADDRESS(INTEGRATOR_SC_BASE) + INTEGRATOR_SC_CTRLS_OFFSET)
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static void integrator_uart_set_mctrl(struct amba_device *dev, void __iomem *base, unsigned int mctrl)
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{
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unsigned int ctrls = 0, ctrlc = 0, rts_mask, dtr_mask;
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if (dev == &uart0_device) {
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rts_mask = 1 << 4;
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dtr_mask = 1 << 5;
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} else {
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rts_mask = 1 << 6;
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dtr_mask = 1 << 7;
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}
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if (mctrl & TIOCM_RTS)
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ctrlc |= rts_mask;
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else
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ctrls |= rts_mask;
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if (mctrl & TIOCM_DTR)
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ctrlc |= dtr_mask;
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else
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ctrls |= dtr_mask;
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__raw_writel(ctrls, SC_CTRLS);
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__raw_writel(ctrlc, SC_CTRLC);
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}
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static struct amba_pl010_data integrator_uart_data = {
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.set_mctrl = integrator_uart_set_mctrl,
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};
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#define CM_CTRL IO_ADDRESS(INTEGRATOR_HDR_BASE) + INTEGRATOR_HDR_CTRL_OFFSET
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static DEFINE_SPINLOCK(cm_lock);
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/**
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* cm_control - update the CM_CTRL register.
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* @mask: bits to change
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* @set: bits to set
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*/
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void cm_control(u32 mask, u32 set)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&cm_lock, flags);
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val = readl(CM_CTRL) & ~mask;
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writel(val | set, CM_CTRL);
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spin_unlock_irqrestore(&cm_lock, flags);
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}
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EXPORT_SYMBOL(cm_control);
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/*
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* Where is the timer (VA)?
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*/
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#define TIMER0_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000000)
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#define TIMER1_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000100)
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#define TIMER2_VA_BASE (IO_ADDRESS(INTEGRATOR_CT_BASE)+0x00000200)
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/*
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* How long is the timer interval?
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*/
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#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
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#if TIMER_INTERVAL >= 0x100000
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#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
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#elif TIMER_INTERVAL >= 0x10000
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#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
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#else
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#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
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#endif
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static unsigned long timer_reload;
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static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE;
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static cycle_t timersp_read(struct clocksource *cs)
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{
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return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff);
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}
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static struct clocksource clocksource_timersp = {
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.name = "timer2",
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.rating = 200,
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.read = timersp_read,
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.mask = CLOCKSOURCE_MASK(16),
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.shift = 16,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void integrator_clocksource_init(u32 khz)
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{
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struct clocksource *cs = &clocksource_timersp;
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void __iomem *base = clksrc_base;
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u32 ctrl = TIMER_CTRL_ENABLE;
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if (khz >= 1500) {
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khz /= 16;
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ctrl = TIMER_CTRL_DIV16;
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}
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writel(ctrl, base + TIMER_CTRL);
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writel(0xffff, base + TIMER_LOAD);
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cs->mult = clocksource_khz2mult(khz, cs->shift);
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clocksource_register(cs);
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}
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static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
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/*
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* IRQ handler for the timer
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*/
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static irqreturn_t integrator_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* clear the interrupt */
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writel(1, clkevt_base + TIMER_INTCLR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static void clkevt_set_mode(enum clock_event_mode mode, struct clock_event_device *evt)
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{
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u32 ctrl = readl(clkevt_base + TIMER_CTRL) & ~TIMER_CTRL_ENABLE;
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BUG_ON(mode == CLOCK_EVT_MODE_ONESHOT);
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if (mode == CLOCK_EVT_MODE_PERIODIC) {
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writel(ctrl, clkevt_base + TIMER_CTRL);
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writel(timer_reload, clkevt_base + TIMER_LOAD);
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ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
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}
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writel(ctrl, clkevt_base + TIMER_CTRL);
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}
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static int clkevt_set_next_event(unsigned long next, struct clock_event_device *evt)
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{
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unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
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writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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writel(next, clkevt_base + TIMER_LOAD);
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writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
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return 0;
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}
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static struct clock_event_device integrator_clockevent = {
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.name = "timer1",
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.shift = 34,
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.features = CLOCK_EVT_FEAT_PERIODIC,
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.set_mode = clkevt_set_mode,
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.set_next_event = clkevt_set_next_event,
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.rating = 300,
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.cpumask = cpu_all_mask,
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};
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static struct irqaction integrator_timer_irq = {
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.name = "timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = integrator_timer_interrupt,
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.dev_id = &integrator_clockevent,
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};
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static void integrator_clockevent_init(u32 khz, unsigned int ctrl)
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{
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struct clock_event_device *evt = &integrator_clockevent;
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if (khz * 1000 > 0x100000 * HZ) {
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khz /= 256;
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ctrl |= TIMER_CTRL_DIV256;
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} else if (khz * 1000 > 0x10000 * HZ) {
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khz /= 16;
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ctrl |= TIMER_CTRL_DIV16;
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}
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timer_reload = khz * 1000 / HZ;
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writel(ctrl, clkevt_base + TIMER_CTRL);
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evt->irq = IRQ_TIMERINT1;
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evt->mult = div_sc(khz, NSEC_PER_MSEC, evt->shift);
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evt->max_delta_ns = clockevent_delta2ns(0xffff, evt);
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evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
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setup_irq(IRQ_TIMERINT1, &integrator_timer_irq);
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clockevents_register_device(evt);
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}
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/*
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* Set up timer(s).
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*/
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void __init integrator_time_init(unsigned long reload, unsigned int ctrl)
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{
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writel(0, TIMER0_VA_BASE + TIMER_CTRL);
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writel(0, TIMER1_VA_BASE + TIMER_CTRL);
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writel(0, TIMER2_VA_BASE + TIMER_CTRL);
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integrator_clocksource_init(reload * HZ / 1000);
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integrator_clockevent_init(reload * HZ / 1000, ctrl);
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}
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