a1900f2efe
OMAP4 DPLL_ABE can enable a 4X multipler on top of the normal MN multipler and divider. This is achieved by setting CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit in CKGEN module of CM1. From the OMAP4 TRM: Fdpll = Fref x 2 x (4 x M/(N+1)) in case REGM4XEN bit field is set (only applicable to DPLL_ABE). Add new round_rate() and recalc() functions for OMAP4, that check the setting of REGM4XEN bit and handle this appropriately. The new functions are a simple wrapper on top of the existing omap2_dpll_round_rate() and omap2_dpll_get_rate() functions to handle the REGM4XEN bit. The REGM4XEN bit is only implemented for the ABE DPLL on OMAP4 and so only dpll_abe_ck uses omap4_dpll_regm4xen_round_rate() and omap4_dpll_regm4xen_recalc() functions. Signed-off-by: Mike Turquette <mturquette@ti.com> Tested-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com> [paul@pwsan.com: fixed attempt to return a negative from a fn returning unsigned; pass along errors from omap2_dpll_round_rate(); added documentation; added Jon's S-o-b] Signed-off-by: Paul Walmsley <paul@pwsan.com>
20 lines
517 B
C
20 lines
517 B
C
/*
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* OMAP4 clock function prototypes and macros
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*
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* Copyright (C) 2009 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
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#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
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/*
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* OMAP4430_REGM4XEN_MULT: If the CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit is
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* set, then the DPLL's lock frequency is multiplied by 4 (OMAP4430 TRM
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* vV Section 3.6.3.3.1 "DPLLs Output Clocks Parameters")
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*/
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#define OMAP4430_REGM4XEN_MULT 4
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int omap4xxx_clk_init(void);
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#endif
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