85cd7467f3
Added devicetree binding documentation for gpios used as chipselect. The code to evaluate these is already present in spi_mpc8xxx.c. Signed-off-by: Ernst Schwab <eschwab@online.de> Reviewed-by: Wolfram Sang <w.sang@pengutronix.de> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
31 lines
1.1 KiB
Text
31 lines
1.1 KiB
Text
* SPI (Serial Peripheral Interface)
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Required properties:
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- cell-index : SPI controller index.
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- compatible : should be "fsl,spi".
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- mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
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- reg : Offset and length of the register set for the device
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- interrupts : <a b> where a is the interrupt number and b is a
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field that represents an encoding of the sense and level
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information for the interrupt. This should be encoded based on
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the information in section 2) depending on the type of interrupt
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controller you have.
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- interrupt-parent : the phandle for the interrupt controller that
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services interrupts for this device.
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Optional properties:
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- gpios : specifies the gpio pins to be used for chipselects.
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The gpios will be referred to as reg = <index> in the SPI child nodes.
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If unspecified, a single SPI device without a chip select can be used.
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Example:
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spi@4c0 {
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <4c0 40>;
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interrupts = <82 0>;
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interrupt-parent = <700>;
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mode = "cpu";
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gpios = <&gpio 18 1 // device reg=<0>
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&gpio 19 1>; // device reg=<1>
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};
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