0c2daaafcd
This patch improves the recovery of the MPC's I2C bus from errors like bus
hangs resulting in timeouts:
1. make the bus timeout configurable, as it depends on the bus clock and
the attached slave chip(s); default is still 1 second;
2. detect any of the cases indicated by the CF, BB and RXAK MSR flags if a
timeout occurs, and add a missing (required) MAL reset;
3. use a more reliable method to fixup the bus if a hang has been detected.
The sequence is sent 9 times which seems to be necessary if a slave
"misses" more than one clock cycle. For 400 kHz bus speed, the fixup is
also ~70us (81us vs. 150us) faster.
Tested on a custom Lite5200b derived board, with a Dallas RTC, AD sensors
and NXP IO expander chips attached to the i2c.
Changes vs. v1:
- use improved bus fixup sequence for all chips (not only the 5200)
- calculate real clock from defaults if no clock is given in the device tree
- better description (I hope) of the changes.
I didn't split the changes in this file into three parts as recommended by
Grant, as they actually belong together (i.e. they address one single
problem, just in three places of one single source file).
Signed-off-by: Albrecht Dreß <albrecht.dress@arcor.de>
[grant.likely@secretlab.ca: fixup for ->node to ->dev.of_node transition]
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
64 lines
1.8 KiB
Text
64 lines
1.8 KiB
Text
* I2C
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Required properties :
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- reg : Offset and length of the register set for the device
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- compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a
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compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121,
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mpc5200 or mpc5200b. For the mpc5121, an additional node
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"fsl,mpc5121-i2c-ctrl" is required as shown in the example below.
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Recommended properties :
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- interrupts : <a b> where a is the interrupt number and b is a
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field that represents an encoding of the sense and level
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information for the interrupt. This should be encoded based on
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the information in section 2) depending on the type of interrupt
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controller you have.
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- interrupt-parent : the phandle for the interrupt controller that
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services interrupts for this device.
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- fsl,preserve-clocking : boolean; if defined, the clock settings
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from the bootloader are preserved (not touched).
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- clock-frequency : desired I2C bus clock frequency in Hz.
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- fsl,timeout : I2C bus timeout in microseconds.
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Examples :
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/* MPC5121 based board */
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i2c@1740 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5121-i2c", "fsl-i2c";
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reg = <0x1740 0x20>;
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interrupts = <11 0x8>;
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interrupt-parent = <&ipic>;
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clock-frequency = <100000>;
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};
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i2ccontrol@1760 {
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compatible = "fsl,mpc5121-i2c-ctrl";
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reg = <0x1760 0x8>;
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};
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/* MPC5200B based board */
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i2c@3d00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
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reg = <0x3d00 0x40>;
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interrupts = <2 15 0>;
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interrupt-parent = <&mpc5200_pic>;
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fsl,preserve-clocking;
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};
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/* MPC8544 base board */
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i2c@3100 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,mpc8544-i2c", "fsl-i2c";
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reg = <0x3100 0x100>;
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interrupts = <43 2>;
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interrupt-parent = <&mpic>;
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clock-frequency = <400000>;
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fsl,timeout = <10000>;
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};
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