10b98527c3
This patch updates the documentation for ASoC to reflect the recent changes in API between 0.12.x and 0.13.x Changes:- o Removed all reference to old API's. o Removed references and examples of automatic DAI config and matching. o Fixed 80 char line length on some files. Signed-off-by: Liam Girdwood <lg@opensource.wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
56 lines
2.2 KiB
Text
56 lines
2.2 KiB
Text
ASoC currently supports the three main Digital Audio Interfaces (DAI) found on
|
|
SoC controllers and portable audio CODECS today, namely AC97, I2S and PCM.
|
|
|
|
|
|
AC97
|
|
====
|
|
|
|
AC97 is a five wire interface commonly found on many PC sound cards. It is
|
|
now also popular in many portable devices. This DAI has a reset line and time
|
|
multiplexes its data on its SDATA_OUT (playback) and SDATA_IN (capture) lines.
|
|
The bit clock (BCLK) is always driven by the CODEC (usually 12.288MHz) and the
|
|
frame (FRAME) (usually 48kHz) is always driven by the controller. Each AC97
|
|
frame is 21uS long and is divided into 13 time slots.
|
|
|
|
The AC97 specification can be found at :-
|
|
http://www.intel.com/design/chipsets/audio/ac97_r23.pdf
|
|
|
|
|
|
I2S
|
|
===
|
|
|
|
I2S is a common 4 wire DAI used in HiFi, STB and portable devices. The Tx and
|
|
Rx lines are used for audio transmision, whilst the bit clock (BCLK) and
|
|
left/right clock (LRC) synchronise the link. I2S is flexible in that either the
|
|
controller or CODEC can drive (master) the BCLK and LRC clock lines. Bit clock
|
|
usually varies depending on the sample rate and the master system clock
|
|
(SYSCLK). LRCLK is the same as the sample rate. A few devices support separate
|
|
ADC and DAC LRCLK's, this allows for similtanious capture and playback at
|
|
different sample rates.
|
|
|
|
I2S has several different operating modes:-
|
|
|
|
o I2S - MSB is transmitted on the falling edge of the first BCLK after LRC
|
|
transition.
|
|
|
|
o Left Justified - MSB is transmitted on transition of LRC.
|
|
|
|
o Right Justified - MSB is transmitted sample size BCLK's before LRC
|
|
transition.
|
|
|
|
PCM
|
|
===
|
|
|
|
PCM is another 4 wire interface, very similar to I2S, that can support a more
|
|
flexible protocol. It has bit clock (BCLK) and sync (SYNC) lines that are used
|
|
to synchronise the link whilst the Tx and Rx lines are used to transmit and
|
|
receive the audio data. Bit clock usually varies depending on sample rate
|
|
whilst sync runs at the sample rate. PCM also supports Time Division
|
|
Multiplexing (TDM) in that several devices can use the bus similtaniuosly (This
|
|
is sometimes referred to as network mode).
|
|
|
|
Common PCM operating modes:-
|
|
|
|
o Mode A - MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
|
|
|
|
o Mode B - MSB is transmitted on rising edge of FRAME/SYNC.
|