f2f5f2a1ce
Add a bool in ath9k_platform_data to pass AHB clock speed information. Driver needs this to configure PLL on some SOCs. Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
35 lines
1.2 KiB
C
35 lines
1.2 KiB
C
/*
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* Copyright (c) 2008 Atheros Communications Inc.
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* Copyright (c) 2009 Gabor Juhos <juhosg@openwrt.org>
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* Copyright (c) 2009 Imre Kaloz <kaloz@openwrt.org>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _LINUX_ATH9K_PLATFORM_H
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#define _LINUX_ATH9K_PLATFORM_H
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#define ATH9K_PLAT_EEP_MAX_WORDS 2048
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struct ath9k_platform_data {
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u16 eeprom_data[ATH9K_PLAT_EEP_MAX_WORDS];
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u8 *macaddr;
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int led_pin;
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u32 gpio_mask;
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u32 gpio_val;
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bool is_clk_25mhz;
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};
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#endif /* _LINUX_ATH9K_PLATFORM_H */
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