3f84622d7c
The nvram_get function was never in the mainline kernel, it only existed in an external OpenWrt patch. Use nvram_getenv function, which is in mainline and use an include instead of an extra function declaration. et0macaddr contains the mac address in text from like 00:11:22:33:44:55. We have to parse it before adding it into macaddr. nvram_parse_macaddr will be merged into asm/mach-bcm47xx/nvram.h through the MIPS git tree and will be available soon. It will not build now without nvram_parse_macaddr, but it hasn't before either. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> To: linux-mips@linux-mips.org Cc: mb@bu3sch.de Cc: netdev@vger.kernel.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Michael Buesch <mb@bu3sch.de> Patchwork: https://patchwork.linux-mips.org/patch/1849/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
179 lines
4.9 KiB
C
179 lines
4.9 KiB
C
#ifndef LINUX_SSB_DRIVER_GIGE_H_
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#define LINUX_SSB_DRIVER_GIGE_H_
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#include <linux/ssb/ssb.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#ifdef CONFIG_SSB_DRIVER_GIGE
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#define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
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#define SSB_GIGE_RESERVED 0x0400 /* Reserved (1024 bytes) */
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#define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
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#define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
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#define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
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#define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
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#define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
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#define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
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#define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
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/* TM Status High flags */
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#define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
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/* TM Status Low flags */
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#define SSB_GIGE_TMSLOW_TXBYPASS 0x00080000 /* TX bypass (no delay) */
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#define SSB_GIGE_TMSLOW_RXBYPASS 0x00100000 /* RX bypass (no delay) */
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#define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
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/* Boardflags (low) */
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#define SSB_GIGE_BFL_ROBOSWITCH 0x0010
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#define SSB_GIGE_MEM_RES_NAME "SSB Broadcom 47xx GigE memory"
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#define SSB_GIGE_IO_RES_NAME "SSB Broadcom 47xx GigE I/O"
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struct ssb_gige {
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struct ssb_device *dev;
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spinlock_t lock;
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/* True, if the device has an RGMII bus.
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* False, if the device has a GMII bus. */
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bool has_rgmii;
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/* The PCI controller device. */
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struct pci_controller pci_controller;
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struct pci_ops pci_ops;
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struct resource mem_resource;
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struct resource io_resource;
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};
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/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
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extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
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/* Convert a pci_dev pointer to a ssb_gige pointer. */
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static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
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{
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if (!pdev_is_ssb_gige_core(pdev))
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return NULL;
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return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
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}
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/* Returns whether the PHY is connected by an RGMII bus. */
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static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
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{
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struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
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return (dev ? dev->has_rgmii : 0);
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}
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/* Returns whether we have a Roboswitch. */
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static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
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{
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struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
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if (dev)
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return !!(dev->dev->bus->sprom.boardflags_lo &
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SSB_GIGE_BFL_ROBOSWITCH);
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return 0;
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}
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/* Returns whether we can only do one DMA at once. */
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static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
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{
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struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
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if (dev)
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return ((dev->dev->bus->chip_id == 0x4785) &&
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(dev->dev->bus->chip_rev < 2));
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return 0;
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}
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/* Returns whether we must flush posted writes. */
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static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
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{
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struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
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if (dev)
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return (dev->dev->bus->chip_id == 0x4785);
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return 0;
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}
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#ifdef CONFIG_BCM47XX
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#include <asm/mach-bcm47xx/nvram.h>
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/* Get the device MAC address */
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static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
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{
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char buf[20];
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if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
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return;
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nvram_parse_macaddr(buf, macaddr);
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}
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#else
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static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
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{
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}
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#endif
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extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
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struct pci_dev *pdev);
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extern int ssb_gige_map_irq(struct ssb_device *sdev,
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const struct pci_dev *pdev);
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/* The GigE driver is not a standalone module, because we don't have support
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* for unregistering the driver. So we could not unload the module anyway. */
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extern int ssb_gige_init(void);
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static inline void ssb_gige_exit(void)
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{
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/* Currently we can not unregister the GigE driver,
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* because we can not unregister the PCI bridge. */
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BUG();
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}
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#else /* CONFIG_SSB_DRIVER_GIGE */
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/* Gigabit Ethernet driver disabled */
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static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
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struct pci_dev *pdev)
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{
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return -ENOSYS;
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}
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static inline int ssb_gige_map_irq(struct ssb_device *sdev,
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const struct pci_dev *pdev)
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{
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return -ENOSYS;
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}
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static inline int ssb_gige_init(void)
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{
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return 0;
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}
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static inline void ssb_gige_exit(void)
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{
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}
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static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
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{
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return 0;
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}
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static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
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{
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return NULL;
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}
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static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
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{
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return 0;
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}
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static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
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{
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return 0;
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}
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static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
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{
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return 0;
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}
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static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
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{
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return 0;
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}
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#endif /* CONFIG_SSB_DRIVER_GIGE */
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#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
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