569712b2b0
Impact: fix secondary-CPU wakeup/init path with numaq and es7000
While looking at wakeup_secondary_cpu for WAKE_SECONDARY_VIA_NMI:
|#ifdef WAKE_SECONDARY_VIA_NMI
|/*
| * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
| * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
| * won't ... remember to clear down the APIC, etc later.
| */
|static int __devinit
|wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip)
|{
| unsigned long send_status, accept_status = 0;
| int maxlvt;
|...
| if (APIC_INTEGRATED(apic_version[phys_apicid])) {
| maxlvt = lapic_get_maxlvt();
I noticed that there is no warning about undefined phys_apicid...
because WAKE_SECONDARY_VIA_NMI and WAKE_SECONDARY_VIA_INIT can not be
defined at the same time. So NUMAQ is using wrong wakeup_secondary_cpu.
WAKE_SECONDARY_VIA_NMI, WAKE_SECONDARY_VIA_INIT and
WAKE_SECONDARY_VIA_MIP are variants of a weird and fragile
preprocessor-driven "HAL" mechanisms to specify the kind of secondary-CPU
wakeup strategy a given x86 kernel will use.
The vast majority of systems want to use INIT for secondary wakeup - NUMAQ
uses an NMI, (old-style-) ES7000 uses 'MIP' (a firmware driven in-memory
flag to let secondaries continue).
So convert these mechanisms to x86_quirks and add a
->wakeup_secondary_cpu() method to specify the rare exception
to the sane default.
Extend genapic accordingly as well, for 32-bit.
While looking further, I noticed that functions in wakecup.h for numaq
and es7000 are different to the default in mach_wakecpu.h - but smpboot.c
will only use default mach_wakecpu.h with smphook.h.
So we need to add mach_wakecpu.h for mach_generic, to properly support
numaq and es7000, and vectorize the following SMP init methods:
int trampoline_phys_low;
int trampoline_phys_high;
void (*wait_for_init_deassert)(atomic_t *deassert);
void (*smp_callin_clear_local_apic)(void);
void (*store_NMI_vector)(unsigned short *high, unsigned short *low);
void (*restore_NMI_vector)(unsigned short *high, unsigned short *low);
void (*inquire_remote_apic)(int apicid);
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
137 lines
2.8 KiB
C
137 lines
2.8 KiB
C
#ifndef __ASM_MACH_APIC_H
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#define __ASM_MACH_APIC_H
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#define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu))
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#define esr_disable (1)
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static inline int apic_id_registered(void)
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{
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return (1);
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}
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static inline cpumask_t target_cpus(void)
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{
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#ifdef CONFIG_SMP
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return cpu_online_map;
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#else
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return cpumask_of_cpu(0);
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#endif
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}
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#undef APIC_DEST_LOGICAL
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#define APIC_DEST_LOGICAL 0
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#define APIC_DFR_VALUE (APIC_DFR_FLAT)
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#define INT_DELIVERY_MODE (dest_Fixed)
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#define INT_DEST_MODE (0) /* phys delivery to target proc */
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#define NO_BALANCE_IRQ (0)
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static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
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{
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return (0);
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}
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static inline unsigned long check_apicid_present(int bit)
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{
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return (1);
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}
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static inline unsigned long calculate_ldr(int cpu)
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{
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unsigned long val, id;
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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id = xapic_phys_to_log_apicid(cpu);
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val |= SET_APIC_LOGICAL_ID(id);
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return val;
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}
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/*
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* Set up the logical destination ID.
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*
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* Intel recommends to set DFR, LDR and TPR before enabling
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* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
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* document number 292116). So here it goes...
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*/
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static inline void init_apic_ldr(void)
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{
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unsigned long val;
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int cpu = smp_processor_id();
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apic_write(APIC_DFR, APIC_DFR_VALUE);
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val = calculate_ldr(cpu);
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apic_write(APIC_LDR, val);
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}
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static inline void setup_apic_routing(void)
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{
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printk("Enabling APIC mode: %s. Using %d I/O APICs\n",
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"Physflat", nr_ioapics);
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}
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static inline int multi_timer_check(int apic, int irq)
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{
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return (0);
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}
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static inline int apicid_to_node(int logical_apicid)
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{
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return apicid_2_node[hard_smp_processor_id()];
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}
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static inline int cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < NR_CPUS)
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return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
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return BAD_APICID;
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}
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static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
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{
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return physid_mask_of_physid(phys_apicid);
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}
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extern u8 cpu_2_logical_apicid[];
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/* Mapping from cpu number to logical apicid */
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static inline int cpu_to_logical_apicid(int cpu)
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{
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if (cpu >= NR_CPUS)
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return BAD_APICID;
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return cpu_physical_id(cpu);
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}
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static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
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{
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/* For clustered we don't have a good way to do this yet - hack */
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return physids_promote(0xFFL);
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}
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static inline void setup_portio_remap(void)
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{
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}
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static inline void enable_apic_mode(void)
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{
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}
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static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return (1);
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}
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/* As we are using single CPU as destination, pick only one CPU here */
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static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
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{
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int cpu;
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int apicid;
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cpu = first_cpu(cpumask);
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apicid = cpu_to_logical_apicid(cpu);
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return apicid;
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}
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static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
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{
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return cpuid_apic >> index_msb;
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}
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#endif /* __ASM_MACH_APIC_H */
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