0d90c3ac0b
ERR_{,UN}CORRECTABLE_ERROR_MASK are set of error bits which linux know,
set of PCI_ERR_COR_* and PCI_ERR_UNC_* defined in linux/pci_regs.h.
This masks make aerdrv not to report errors of unknown bit, while aerdrv
have ability to report such undefined errors as "Unknown Error Bit %2d".
OTOH aerdrv_errprint does not have any check of setting in mask register.
So it could report masked wrong error by finding bit in status without
knowing that the bit is masked in the mask register.
This patch changes aerdrv to use mask state in mask register propely
instead of defined/hardcoded ERR_{,UN}CORRECTABLE_ERROR_MASK.
This change prevents aerdrv from reporting masked error, and also enable
reporting unknown errors.
Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>
Reviewed-by: Andrew Patterson <andrew.patterson@hp.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
137 lines
3.3 KiB
C
137 lines
3.3 KiB
C
/*
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* Copyright (C) 2006 Intel Corp.
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* Tom Long Nguyen (tom.l.nguyen@intel.com)
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* Zhang Yanmin (yanmin.zhang@intel.com)
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*
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*/
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#ifndef _AERDRV_H_
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#define _AERDRV_H_
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#include <linux/workqueue.h>
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#include <linux/pcieport_if.h>
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#include <linux/aer.h>
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#include <linux/interrupt.h>
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#define AER_NONFATAL 0
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#define AER_FATAL 1
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#define AER_CORRECTABLE 2
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#define AER_UNCORRECTABLE 4
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#define AER_ERROR_MASK 0x001fffff
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#define AER_ERROR(d) (d & AER_ERROR_MASK)
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/* Root Error Status Register Bits */
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#define ROOT_ERR_STATUS_MASKS 0x0f
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#define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
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PCI_EXP_RTCTL_SENFEE| \
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PCI_EXP_RTCTL_SEFEE)
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#define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
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PCI_ERR_ROOT_CMD_NONFATAL_EN| \
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PCI_ERR_ROOT_CMD_FATAL_EN)
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#define ERR_COR_ID(d) (d & 0xffff)
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#define ERR_UNCOR_ID(d) (d >> 16)
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#define AER_SUCCESS 0
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#define AER_UNSUCCESS 1
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#define AER_ERROR_SOURCES_MAX 100
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#define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
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PCI_ERR_UNC_ECRC| \
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PCI_ERR_UNC_UNSUP| \
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PCI_ERR_UNC_COMP_ABORT| \
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PCI_ERR_UNC_UNX_COMP| \
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PCI_ERR_UNC_MALF_TLP)
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/* AER Error Info Flags */
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#define AER_TLP_HEADER_VALID_FLAG 0x00000001
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#define AER_MULTI_ERROR_VALID_FLAG 0x00000002
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struct header_log_regs {
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unsigned int dw0;
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unsigned int dw1;
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unsigned int dw2;
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unsigned int dw3;
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};
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#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
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struct aer_err_info {
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struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
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int error_dev_num;
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u16 id;
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int severity; /* 0:NONFATAL | 1:FATAL | 2:COR */
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int flags;
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unsigned int status; /* COR/UNCOR Error Status */
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unsigned int mask; /* COR/UNCOR Error Mask */
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struct header_log_regs tlp; /* TLP Header */
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};
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struct aer_err_source {
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unsigned int status;
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unsigned int id;
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};
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struct aer_rpc {
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struct pcie_device *rpd; /* Root Port device */
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struct work_struct dpc_handler;
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struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
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unsigned short prod_idx; /* Error Producer Index */
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unsigned short cons_idx; /* Error Consumer Index */
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int isr;
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spinlock_t e_lock; /*
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* Lock access to Error Status/ID Regs
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* and error producer/consumer index
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*/
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struct mutex rpc_mutex; /*
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* only one thread could do
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* recovery on the same
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* root port hierarchy
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*/
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wait_queue_head_t wait_release;
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};
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struct aer_broadcast_data {
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enum pci_channel_state state;
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enum pci_ers_result result;
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};
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static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
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enum pci_ers_result new)
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{
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if (new == PCI_ERS_RESULT_NONE)
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return orig;
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switch (orig) {
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case PCI_ERS_RESULT_CAN_RECOVER:
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case PCI_ERS_RESULT_RECOVERED:
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orig = new;
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break;
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case PCI_ERS_RESULT_DISCONNECT:
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if (new == PCI_ERS_RESULT_NEED_RESET)
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orig = new;
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break;
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default:
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break;
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}
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return orig;
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}
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extern struct bus_type pcie_port_bus_type;
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extern void aer_enable_rootport(struct aer_rpc *rpc);
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extern void aer_delete_rootport(struct aer_rpc *rpc);
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extern int aer_init(struct pcie_device *dev);
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extern void aer_isr(struct work_struct *work);
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extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
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extern irqreturn_t aer_irq(int irq, void *context);
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#ifdef CONFIG_ACPI
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extern int aer_osc_setup(struct pcie_device *pciedev);
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#else
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static inline int aer_osc_setup(struct pcie_device *pciedev)
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{
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return 0;
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}
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#endif
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#endif /* _AERDRV_H_ */
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